Branch Prediction Error Recovery in Return Address Stack
Solution Overview
Problem
Conventional computing devices face performance losses due to branch prediction errors, particularly when re-instruction-fetch is issued out of order, leading to inaccuracies in return address stack predictions and reduced processing rates.
Innovation Solution
A computing device with a pipeline that executes instructions, a queue for call and return instructions, and a processor that stores and manages prediction information to re-execute the closest entry to the top of the queue upon branch prediction errors, ensuring accurate re-instruction-fetch and maintaining pipeline performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If re-instruction-fetch is issued out of order to hide pipeline delays, then processing speed is improved, but accuracy of return address stack prediction deteriorates
Solution Approach 1:
The patent applies preliminary action by performing push operations for call instructions before issuing the re-instruction-fetch request. When a branch prediction error is detected, the system proactively pushes return addresses onto the RAS fetch stack for all call instructions that appear before the erroneous branch instruction in the queue, even if those call instructions have not yet completed execution. This ensures that when the out-of-order re-instruction-fetch occurs, the RAS fetch stack already contains the correct return addresses, maintaining prediction accuracy while enabling speed improvement through out-of-order processing.
2Measurement precision
If re-instruction-fetch is issued in order to maintain prediction accuracy, then branch prediction accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The patent applies dynamics by making the RAS fetch stack management adaptive to the out-of-order execution flow. Instead of a fixed in-order processing approach, the system dynamically adjusts by: (1) detecting branch prediction errors regardless of execution order, (2) identifying the erroneous branch instruction position in the queue, (3) selectively pushing return addresses for call instructions before the erroneous branch, and (4) issuing the re-instruction-fetch request at the optimal moment. This dynamic adaptation allows the system to maintain prediction accuracy while maximizing processing speed through out-of-order execution.
3Measurement precision
If the processor waits for foregoing branch instructions to complete before issuing re-instruction-fetch, then prediction accuracy is maintained, but loss of time increases
Solution Approach 1:
The patent eliminates pipeline stall time by performing preliminary push operations for call instructions before the erroneous branch instruction. Instead of waiting for foregoing branch instructions to complete, the system proactively prepares the RAS fetch stack with return addresses for all call instructions that appear before the erroneous branch in the queue. This preliminary action ensures that when the re-instruction-fetch is issued immediately upon detecting the branch prediction error, the prediction accuracy is maintained while avoiding any time loss from waiting.
Data Source
AI summary
A processor configured to store prediction information that is obtained from a call instruction that is fetched in a RAS fetch, acquire the prediction information that is used in a return instruction from the RAS fetch, delete the prediction information, store the prediction information in a RAS complete after completion of execution of the call instruction, and delete the prediction information from the RAS complete after completion of execution of the return instruction, and specify a first entry that is the closest to a top of the queue among the entries in which the branch instruction on which the branch prediction error is detected is re-executed, store and delete the prediction information in and from the RAS fetch according to the call instruction and the return instruction that are stored in entries closer to the top than the first entry is, and cause the first entry to be re-executes.