Branch Prediction Circuitry for Multi-Target Fetch Queues

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Solution Overview

Problem

Existing branch prediction mechanisms often discard useful predictions for branch instructions that branch within the same block of instructions, leading to inefficiencies in data processing systems.

Innovation Solution

The proposed branch prediction circuitry generates predictions for multiple branch targets within a single block of sequential instructions, using determination circuitry to identify conditions that allow for predicting branch targets for both the selected branch and further branch instructions, reducing the frequency of discarded predictions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If branch prediction circuitry generates predictions for only the selected branch instruction, then the prediction mechanism remains simple, but useful predictions for further branch instructions within the same block are discarded

Engineering Contradiction:
Improvebranch prediction efficiencyVSAvoidprediction generation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The branch prediction circuitry performs preliminary actions by generating predictions for multiple branch instructions within a block before execution begins. The determination circuitry evaluates conditions (such as branch target being within the same block) in advance to identify which predictions should be retained, allowing the fetch queue to be populated with multiple predicted branch targets rather than discarding them after single prediction generation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the branch prediction process into distinct components: branch target prediction circuitry that generates predictions, determination circuitry that evaluates conditions, and selection logic that identifies which predictions to retain. This segmentation allows the system to handle multiple branch instructions within a block systematically, generating predictions for each branch while managing complexity through modular processing

Inventive Principle:
Principle #1Segmentation

2Loss of information

If the fetch queue is populated with multiple predicted branch targets, then the number of discarded predictions is reduced, but the complexity of determining which predictions to generate increases

Engineering Contradiction:
Improveprediction discard rateVSAvoiddetermination logic complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The determination circuitry applies local quality by evaluating specific conditions for each branch instruction within the block. Instead of uniformly treating all branches the same, the system examines local characteristics such as whether the branch target is within the same block, and adjusts prediction generation accordingly. This allows selective retention of predictions based on their specific properties rather than applying a blanket discard policy

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12405797B2Branch prediction circuitry
Publication Date: 2025.09.02 ARM LTD
  • US12405797B2 patent drawing
  • US12405797B2 patent drawing
  • US12405797B2 patent drawing

AI summary

Branch prediction circuitry comprising branch target prediction circuitry to, for an identified block of sequential instructions, generate a branch target prediction identifying a predicted branch target for a selected branch instruction in the block of sequential instructions; output circuitry to output the branch target prediction; and determination circuitry to determine whether at least one condition is met. The branch target prediction circuitry is responsive to the determination circuitry determining that the at least one condition is met to generate the branch target prediction to identify both the predicted branch target for the selected branch instruction and one or more further predicted branch targets for one or more further branch instructions in the block of sequential instructions.