Branch Prediction Circuit Using Load Data Accordance

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Solution Overview

Problem

Existing processor devices face a decrease in branch destination prediction hit rate in machine control systems where loop processing is frequently changed due to external control signals, leading to pipeline stalls and reduced performance.

Innovation Solution

A processor device with a branch prediction circuit that uses an equivalent value judgment circuit and judgment history record circuit to predict whether the branch destination will be the same or different based on previous execution results, and a buffer update circuit that adjusts the history mask to exclude irrelevant variables, improving prediction accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a simple branch destination buffer is used for prediction, then the device complexity is low, but the prediction hit rate decreases when loop processing is frequently changed due to external control signals

Engineering Contradiction:
Improvebranch destination prediction hit rateVSAvoidprediction circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The prediction system is segmented into multiple independent components: a branch destination buffer for storing historical prediction data, an equivalent value judgment circuit for comparing load data, a judgment history record circuit for tracking comparison results, and a buffer update circuit for maintaining prediction accuracy. Each component handles a specific aspect of the prediction process, allowing the system to adapt to varying loop processing patterns while maintaining manageable complexity through modular design.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the branch prediction always predicts the same destination as previous execution, then the prediction circuit is simple, but the prediction accuracy decreases when loop processing changes due to external control signals

Engineering Contradiction:
Improveprediction accuracyVSAvoidprediction circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The prediction system dynamically adapts to changing loop processing patterns by incorporating the equivalent value judgment circuit that compares previous and present load data, and the judgment history record circuit that tracks comparison results. This dynamic adjustment mechanism allows the prediction accuracy to improve when data patterns change, while the overall circuit complexity remains controlled through systematic design of the adaptive components.

Inventive Principle:
Principle #15Dynamics

3Reliability

If no data comparison is performed before branch prediction, then the processing speed is fast, but the prediction hit rate decreases when external control signals frequently change loop processing

Engineering Contradiction:
Improveprediction hit rateVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The equivalent value judgment circuit performs preliminary comparison of previous and present load data before the branch prediction is made. This preliminary action of comparing data equivalence allows the system to anticipate whether loop processing will continue or change, thereby improving prediction hit rate without significantly impacting processing speed since the comparison is integrated into the existing data flow.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11126435B2Branch destination prediction based on accord or discord of previous load data from a data cache line corresponding to a load instruction and present load data
Publication Date: 2021.09.21 RENESAS ELECTRONICS CORP
  • US11126435B2 patent drawing
  • US11126435B2 patent drawing
  • US11126435B2 patent drawing

AI summary

A processor device capable of raising a hit rate of branch destination prediction is provided. Every time a load instruction to a data cache is generated, an equivalent value judgment circuit judges accord/disaccord of present load data and previous load data from a corresponding line. In an N bit region, as history records, a judgment history record circuit records judgment results of N times by the equivalent value judgment circuit before a conditional branch instruction is generated. When the conditional branch instruction is generated, based on the history records in the N bit region, a branch prediction circuit predicts the same branch destination as the previous branch destination obtained by a previous execution result of the conditional branch instruction or a branch destination different from the previous destination. Further, the branch prediction circuit issues an instruction fetch direction of the predicted branch destination to a processor main-body circuit.