Branch Prediction Pipeline Access Control for Pattern History Table Latency
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Solution Overview
Problem
Existing branch prediction devices face delays due to hash logic circuits located immediately before pattern history tables, which impede processing speed and increase clock cycles, as they cannot perform operations until the branch command address is known during the fetch stage, leading to delays in accessing pattern history tables and affecting processor performance.
Innovation Solution
A branch prediction device that uses a pipeline access control section to manage branch prediction information accumulation and selection, allowing for pipelined processing of branch prediction groups and index information control, enabling selection and prediction result generation without the need for hash logic circuits immediately before pattern history tables, thus reducing delays and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hash logic circuits are provided immediately before pattern history tables, then branch prediction accuracy is maintained, but processing delay increases and clock cycles are extended
Solution Approach 1:
The pattern history table access is divided into multiple pipeline stages: hash calculation stage, table access stage, and prediction result generation stage. This segmentation allows each stage to be optimized independently and enables parallel processing of different branch predictions across stages, reducing overall delay while maintaining accuracy.
Solution Approach 2:
Hash calculations are performed in advance during earlier pipeline stages before the actual pattern history table access is needed. Index information is pre-computed and prepared, so when the table access stage is reached, the operation can proceed immediately without waiting for hash calculation, thereby reducing critical path delay.
2Measurement precision
If hash logic circuits are placed immediately before pattern history tables, then proper indexing is achieved, but processing speed decreases due to sequential dependency
Solution Approach 1:
Pipeline registers are introduced as intermediaries between the hash logic circuits and the pattern history table. These registers buffer the index information and enable the table access to proceed in the next pipeline stage without waiting for the hash logic to complete, thereby breaking the sequential dependency and improving processing speed while maintaining indexing accuracy.
3Reliability
If hash logic circuits operate after branch command address is known, then correct addressing is ensured, but fetch stage is delayed
Solution Approach 1:
The hash logic circuits are configured to operate in parallel with the fetch stage rather than sequentially after it. Index information is calculated using branch command addresses as soon as they become available, and the results are forwarded through pipeline registers to the pattern history table access stage, ensuring addressing correctness while minimizing fetch stage delay.
Data Source
AI summary
A branch prediction device capable of preventing degradation of branch prediction accuracy and a delay in processing speed is provided. The branch prediction device includes a branch prediction information accumulation processing section which stores branch prediction groups in which a plurality of pieces of branch prediction information are grouped, and performs accumulation-processing of the branch prediction information. The branch prediction device further includes a pipeline access control section which performs processing, upon request, by pipeline processing, including first selection control processing for selection-controlling at least one branch prediction group from the branch prediction groups, and second selection control processing for selection-controlling one or a plurality of pieces of branch prediction information from the branch prediction group, and controls an access to the branch prediction information accumulation processing section.