Branch Prediction Circuit with Segmented Global History Registers
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Solution Overview
Problem
Current microprocessor technologies face challenges in achieving accurate branch prediction, leading to inefficiencies in pipeline processing, increased power dissipation, and reduced performance due to incorrect branch predictions, especially in deeply pipelined and superscalar processors.
Innovation Solution
A processor design that includes a pipeline with a fetch stage and an execute stage, featuring a first storing circuit for actual branch history and a second storing circuit for predicted branch patterns, with the execute stage coupled back to the first storing circuit, allowing for parallel storage and updating of branch data to improve prediction accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If branch prediction is implemented in deeply pipelined processors, then instruction throughput is improved, but power dissipation increases due to incorrect predictions and pipeline flushes
Solution Approach 1:
The branch history is segmented into multiple global history registers (GHR0, GHR1, etc.) instead of using a single register. Each GHR captures branch outcomes from different pipeline stages, allowing the system to track branch patterns at multiple points in the pipeline simultaneously. This segmentation enables more accurate prediction by comparing multiple history perspectives without requiring a single large, power-consuming register.
Solution Approach 2:
The patent adds a temporal dimension to branch history tracking by capturing branch outcomes at multiple pipeline stages (fetch, decode, execute) rather than just at one point. This multi-dimensional history capture allows the predictor to analyze branch patterns from different time points in the pipeline, improving accuracy without proportionally increasing power consumption.
2Measurement precision
If larger global history registers are used to improve branch prediction accuracy, then prediction precision is improved, but device complexity and power consumption increase
Solution Approach 1:
Instead of using one large global history register, the patent divides the history storage into multiple smaller GHRs (GHR0, GHR1, etc.), each capturing branch outcomes from different pipeline stages. This segmentation reduces the complexity of any single register while collectively providing comprehensive branch history for accurate prediction.
Solution Approach 2:
The patent pre-captures branch history at multiple pipeline stages before the branch outcome is final. By recording branch directions at fetch, decode, and execute stages in advance, the system builds a comprehensive history profile early, enabling accurate prediction without requiring complex real-time analysis of large register contents.
3Measurement precision
If multiple global history registers are used to capture branch history from different pipeline stages, then branch prediction accuracy is improved, but the number of components and circuit complexity increase
Solution Approach 1:
Multiple GHRs serve universal functions: each register captures branch history from different pipeline stages, and any GHR can contribute to predicting any branch outcome. This multi-functionality allows the system to use multiple simple registers rather than one complex register, reducing overall circuit complexity while maintaining high prediction accuracy.
Solution Approach 2:
The patent segments the branch history tracking function across multiple dedicated registers (GHR0 for fetch stage, GHR1 for decode stage, etc.), where each segment handles a specific pipeline stage. This functional segmentation simplifies the design of each individual register while collectively achieving comprehensive branch prediction capability.
Data Source
AI summary
A processor (1700) for processing instructions has a pipeline (1710, 1736, 1740) including a fetch stage (1710) and an execute stage (1870), a first storing circuit (aGHR 2130) associated with said fetch stage (1710) and operable to store a history of actual branches, and a second storing circuit (wGHR 2140) associated with said fetch stage (1710) and operable to store a pattern of predicted branches, said second storing circuit (wGHR 2140) coupled to said first storing circuit (aGHR 2130), said execute stage (1870) coupled back to said first storing circuit (aGHR 2130). Other processors, wireless communications devices, systems, circuits, devices, branch prediction processes and methods of operation, processes of manufacture, and articles of manufacture, as disclosed and claimed.