Branch Prediction Circuit Using Tag Segmentation
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Solution Overview
Problem
Current branch prediction techniques in processors suffer from long latency, leading to reduced throughput due to the need for complex arithmetic and increased logic stages, especially when dealing with multiple branch instructions within a single fetch line, which results in inefficient instruction fetching and execution.
Innovation Solution
The proposed solution involves a branch prediction mechanism that uses an address table with a single way, where each fetch line is assigned at least two indexes, allowing for concurrent branch prediction of multiple instructions within a fetch line, reducing the number of logic stages and enabling one-cycle latency by using a second tag for high-order bits to match prediction outcomes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex arithmetic is performed for branch prediction to improve accuracy, then branch prediction accuracy is improved, but latency increases beyond one cycle
Solution Approach 1:
The fetch address is segmented into multiple parts: index bits (including varying instruction address bits) and tag bits (higher-order bits). The address table uses only the index bits for addressing, while the tag bits are used for validation. This segmentation allows the address table to be smaller and faster, achieving one-cycle latency while maintaining prediction accuracy through tag matching.
Solution Approach 2:
The tag bits (higher-order bits of the fetch address) are extracted and stored separately in the address table. During branch prediction, only the index bits are used to access the table, and the extracted tag is compared with the current fetch address tags. This extraction allows faster table access while maintaining prediction accuracy.
2Measurement precision
If complex arithmetic is performed for branch prediction to improve accuracy, then branch prediction accuracy is improved, but device complexity increases
Solution Approach 1:
The address table is designed with a simplified structure that stores only the tag bits (higher-order bits) for each index, rather than storing complete address information. This segmentation reduces the table size and the complexity of address matching logic, enabling implementation with fewer logic stages while maintaining prediction accuracy through tag comparison.
Solution Approach 2:
The higher-order tag bits are extracted from the fetch address and stored in the address table. During prediction, only these extracted tags need to be compared, rather than comparing complete addresses. This extraction simplifies the comparison logic and reduces the number of logic stages required.
3Measurement precision
If branch prediction latency is long, then branch prediction accuracy can be improved through complex arithmetic, but throughput decreases due to gaps in instruction fetch sequence
Solution Approach 1:
The address table is pre-filled with branch destination addresses and their corresponding tag bits during instruction fetch. When a branch instruction is encountered, the prediction is made by comparing the current fetch address tags with the pre-stored tags in the address table. This preliminary action allows immediate prediction without waiting for complex arithmetic to complete, maintaining throughput while achieving accurate prediction.
Solution Approach 2:
The address table stores only the necessary tag bits (higher-order bits) for each index, rather than complete address information. This segmentation reduces the table size and allows faster access during branch prediction, eliminating gaps in the instruction fetch sequence and maintaining high throughput while achieving accurate prediction.
Data Source
AI summary
An arithmetic processing circuit includes an fetch unit configured to generate fetch addresses, an address table configured to store a branch address and a first tag for each of a plurality of indexes, the indexes being a first bit string extracted from a fetch address by including at least one bit among instruction address bits whose values vary within one fetch line, the first tag being a second bit string situated at higher bit positions than the first bit string, an upper tag storage unit configured to store a second tag situated at higher bit positions than the first tag, and a branch determination unit configured to supply to the fetch unit the branch address retrieved from the address table, upon determining that the first tag retrieved from the address table and the second tag in the upper tag storage unit match respective portions of the fetch address.