Branch Prediction Unit Power Optimization via Segmented Search
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Solution Overview
Problem
Existing branch prediction methods in high-performance computer processing units are power-consuming and inefficient, particularly when dealing with parallel predictions of branch taking and branch targets, especially in pipelined processors where incorrect predictions lead to significant performance degradation and pipeline stalls.
Innovation Solution
A branch prediction unit that autonomously searches a pattern history memory to identify predicted taken branch instructions, using a search program counter to find branch indicators and retrieve branch source addresses, which are then used to index a branch target buffer only when necessary, reducing unnecessary accesses and operating independently of the instruction fetch unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel prediction of branch taking and branch target is performed, then prediction accuracy is improved, but power consumption increases
Solution Approach 1:
The branch prediction process is segmented into two independent stages: first predicting whether the branch is taken, and only if taken, then predicting the branch target address. This segmentation allows the system to avoid performing the power-consuming branch target prediction when the branch is not taken, thus reducing overall power consumption while maintaining prediction accuracy for taken branches.
Solution Approach 2:
The system performs only the necessary branch target prediction - specifically, it performs branch target prediction only when the branch is predicted to be taken. This partial action approach avoids the excessive power consumption of performing branch target prediction for all branches, including those that are not taken, while still providing accurate predictions when needed.
2Reliability
If branch target buffer is accessed for all branch instructions, then branch target prediction is available, but unnecessary accesses increase power consumption and reduce efficiency
Solution Approach 1:
The branch target buffer is accessed only partially - specifically, only when a branch instruction is predicted to be taken. This selective access pattern eliminates unnecessary buffer accesses for non-taken branches, reducing power consumption and improving prediction efficiency while ensuring the branch target is available when actually needed.
3Speed
If pipeline depth is increased to improve clock frequency, then processing speed is improved, but misprediction penalty increases
Solution Approach 1:
The system implements feedback mechanisms where branch prediction outcomes are monitored and used to refine future predictions. This feedback approach helps reduce misprediction rates, thereby mitigating the increased misprediction penalty that comes with deeper pipelines, while still allowing the pipeline depth to be increased for higher clock frequencies.
Data Source
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AI summary
A branch prediction unit BPU (500) for prediction of a next taken branch instruction in a processing unit (100). The BPU (500) comprises a pattern history memory (504) comprising branch source addresses and branch indicators; a branch target buffer (506) comprising branch targets; and branch prediction logical circuit (502). By means of a search PC, the circuit finds in the memory a branch indicator indicating a predicted taken branch instruction. The circuit selects a first found branch indicator as an indication of a first predicted taken branch instruction. Using the first found branch indicator, the circuit retrieves from the memory, a branch source address of the first predicted taken branch instruction. When the retrieved branch source address is the branch source address nearest to the search PC, the circuit outputs as next PC a branch target retrieved from the buffer. Then the prediction stops.