Branch Prediction Wrong Guess Instruction Mechanism

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Solution Overview

Problem

Existing prefetching mechanisms in processors face inefficiencies due to unnecessary or redundant execution of prefetch instructions, leading to performance degradation and increased power consumption, especially when data is already in the cache or branch prediction mechanism.

Innovation Solution

The introduction of three new instructions: Branch Wrong Guess (BWG), End Branch Wrong Guess (EBWG), and Invalidate Branch Prediction Entry (IBPE), which dynamically manage branch prediction and cache contents to avoid redundant executions and unused prefetches by intentionally introducing prediction errors and updating branch prediction entries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If prefetching instructions are inserted into a program to load branch information into the cache or branch predictor, then branch prediction accuracy is improved, but unnecessary or redundant execution of these instructions degrades program performance and increases power consumption

Engineering Contradiction:
Improvebranch prediction accuracyVSAvoidprogram performance
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent introduces a new parameter state (wrong guess condition) that changes the execution behavior of prefetching instructions. When the branch predictor makes a wrong guess, subsequent prefetching instructions are suppressed, dynamically adjusting their execution based on prediction accuracy rather than always executing them

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the branch predictor's performance is monitored and used to control the execution of prefetching instructions. The wrong guess condition acts as feedback that suppresses redundant prefetching, creating a closed-loop control system that adapts to actual prediction accuracy

Inventive Principle:
Principle #23Feedback

2Reliability

If many prefetching instructions are inserted to prime the cache and branch prediction mechanism during first execution, then initial performance is improved, but re-executing these instructions during subsequent executions is harmful to performance

Engineering Contradiction:
Improveinitial execution efficiencyVSAvoidsubsequent execution performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent makes the execution of prefetching instructions dynamic rather than static. The instructions are executed conditionally based on the wrong guess condition, allowing the system to adapt its behavior between first execution (where prefetching is needed) and subsequent executions (where prefetching may be redundant)

Inventive Principle:
Principle #15Dynamics

3Reliability

If the processor executes all inserted prefetching instructions, then cache and branch predictor are adequately primed, but power consumption increases due to redundant instruction execution

Engineering Contradiction:
Improvecache priming effectivenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements a mechanism to discard (suppress) redundant prefetching instructions when the wrong guess condition is detected. Instead of executing all inserted prefetching instructions, the system selectively discards those that would be redundant, thereby reducing power consumption while maintaining cache priming effectiveness when needed

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS10338923B2Branch prediction path wrong guess instruction
Publication Date: 2019.07.02 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10338923B2 patent drawing
  • US10338923B2 patent drawing
  • US10338923B2 patent drawing

AI summary

A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.