Branch Predictor Escape Mechanism for Microprocessor Cache

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Solution Overview

Problem

Conventional branch prediction schemes in microprocessors face inefficiencies when handling multiple branch instructions in a single cache line fetch, particularly when a more complex branch instruction is allocated to a side with lower prediction complexity, leading to increased misprediction rates and performance degradation.

Innovation Solution

A microprocessor architecture with three cache memory sides, utilizing two types of conditional branch predictors of different complexities, where a mispredicted conditional branch can be moved from a lower complexity side to a higher complexity side based on a configurable probability, reducing misprediction recurrence and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-sided BTAC structure is used, then the device complexity is reduced, but the ability to handle multiple branch instructions in a cache line fetch is insufficient

Engineering Contradiction:
ImproveBTAC structure complexityVSAvoidHandling multiple branch instructions
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The BTAC is divided into multiple sides (first side, second side, third side), each capable of storing branch instruction information. This segmentation allows the structure to handle multiple branch instructions simultaneously while maintaining manageable complexity through modular organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each side of the BTAC is designed with universal functionality to store and predict branch instructions. The prediction tables on each side can handle different branch instructions using the same basic structure, enabling the system to process multiple branch types without requiring entirely separate mechanisms for each.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If all sides use the same complexity predictor, then the device complexity is minimized, but the prediction accuracy for complex branch instructions deteriorates

Engineering Contradiction:
ImprovePredictor complexity uniformityVSAvoidBranch prediction accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Different sides of the BTAC are assigned different predictor complexities based on local requirements. Sides experiencing complex branch patterns use more sophisticated predictors, while sides with simpler patterns use lighter predictors. This local differentiation optimizes overall prediction accuracy without uniformly increasing complexity across all sides.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically selects which side to use for a given branch instruction based on the branch's characteristics and historical performance. This dynamic allocation allows complex branches to be routed to sophisticated predictors while simple branches use efficient simple predictors, optimizing the balance between complexity and accuracy.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If complex branch instructions are handled by simple predictors, then the device complexity is reduced, but the misprediction rate increases

Engineering Contradiction:
ImprovePredictor configurationVSAvoidMisprediction rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system incorporates feedback mechanisms that monitor prediction accuracy for each side and branch type. When mispredictions are detected, the system can adjust which side handles future branch instructions or trigger updates to prediction tables. This feedback loop ensures that complex branches are progressively routed to more capable predictors, reducing the overall misprediction rate.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The BTAC sides perform self-evaluation of their prediction performance and can autonomously determine when to take over handling of specific branch instructions. This self-service capability allows the system to automatically optimize the allocation of branch handling without external intervention, reducing mispredictions by ensuring complex branches are handled by appropriately complex predictors.

Inventive Principle:
Principle #25Self-service

4Reliability

If multiple complex predictors are used on all sides, then the prediction accuracy is improved, but the device complexity and resource usage increase

Engineering Contradiction:
ImproveBranch prediction accuracyVSAvoidOverall predictor system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system changes the complexity parameter of predictors based on the specific needs of different branch instructions and the performance characteristics of different sides. Rather than using maximum complexity uniformly, the system adjusts predictor complexity parameters dynamically, allocating higher complexity only where needed to maintain accuracy while controlling overall system complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system applies complex prediction mechanisms partially, only to the extent necessary for achieving acceptable accuracy. Simple predictors are used wherever possible, with complex predictors activated only for specific complex branch patterns. This partial application of complexity achieves sufficient prediction accuracy without the full overhead of universal complex prediction.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11614944B2Small branch predictor escape
Publication Date: 2023.03.28 CENTAUR TECHNOLOGY INC
  • US11614944B2 patent drawing
  • US11614944B2 patent drawing
  • US11614944B2 patent drawing

AI summary

In one embodiment, a branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache side that uses the lower complexity conditional branch predictor to one of the two large cache sides that uses the higher complexity conditional branch predictors. The move (write) is achieved according to a configurable probability or chance to escape misprediction recurrence and results in a reduced amount of mispredictions for the given branch instruction.