Branch Predictor Architecture for Pipeline Stall Reduction
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Solution Overview
Problem
Current AI processors and shallow pipeline general-purpose processors lack branch predictors, leading to reduced processing performance and efficiency due to pipeline stalls and flushes caused by branch instructions.
Innovation Solution
A branch prediction method and apparatus that includes a branch predictor with a branch target buffer, an address stack, and a loop buffer, which detects branch instructions, predicts jump addresses, and improves pipeline efficiency by reducing pipeline bubbles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a branch predictor is not included in the processor, then the device complexity is reduced, but the processing performance and efficiency deteriorate due to pipeline stalls and flushes
Solution Approach 1:
The branch predictor is divided into multiple specialized components: a branch target buffer for storing branch information, an address stack for function call/return predictions, and a loop buffer for loop detection. Each component handles specific branch types independently, allowing parallel operation and reducing overall prediction latency while maintaining low complexity
Solution Approach 2:
The branch target buffer pre-stores branch target addresses and branch types during instruction decoding. When a branch instruction is encountered during execution, the prediction is immediately available from pre-computed information, eliminating the need for complex runtime analysis and reducing pipeline stalls
2Device complexity
If a simple branch prediction method is used, then the device complexity is reduced, but the measurement precision of jump address prediction deteriorates
Solution Approach 1:
Different prediction strategies are applied to different branch instruction types based on their characteristics: the address stack uses LIFO ordering for function calls/returns where the return address is deterministic, while the loop buffer uses pattern recognition for loop headers. This specialized approach achieves high accuracy for each branch type without requiring a universally complex prediction mechanism
Solution Approach 2:
The branch target buffer acts as an intermediary structure that pre-processes branch information during instruction decoding and stores it for rapid retrieval during execution. This intermediate storage layer separates the complex analysis phase from the simple retrieval phase, achieving high prediction accuracy with minimal execution-time complexity
3Device complexity
If branch instructions are executed without prediction, then the device complexity is reduced, but the loss of time increases due to pipeline stalls and flushes
Solution Approach 1:
Branch target addresses and prediction outcomes are computed and stored during the instruction decoding phase, before execution begins. When the branch instruction reaches the execution stage, the predicted target is already available, allowing the pipeline to continue fetching instructions without stalling, thus eliminating time loss while keeping the execution mechanism simple
Solution Approach 2:
The multiplexer continuously selects between sequential instruction addresses and predicted branch targets based on branch detection results. This ensures the instruction pipeline maintains continuous operation by immediately switching to the correct next instruction address without interruption, preventing pipeline flushes and maintaining uninterrupted useful action
Data Source
AI summary
A branch prediction method includes obtaining an instruction block containing an instruction, performing detection on the instruction block according to branch instruction information stored in a branch target buffer of a branch predictor of a processor, and in response to detecting that the instruction is a branch instruction, detecting a type of the branch instruction. The method further includes, in response to the type of the branch instruction being a type other than a target type, searching for a predicted jump address of the branch instruction in the branch target buffer, and, in response to the type of the branch instruction being the target type, searching for the predicted jump address of the branch instruction in other address areas of the branch predictor. The target type includes at least one of a function call instruction type, a function return instruction type, or a loop instruction type.