Branch Presence Predictor Mitigates Lookahead Branch Prediction Latency

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Solution Overview

Problem

Current processor pipeline systems face latency issues due to branch prediction delays, particularly in lookahead branch prediction, where the Branch Target Buffer (BTB) struggles to keep up with the instruction stream, leading to inaccurate predictions and increased complexity in hierarchical and cascading predictor structures.

Innovation Solution

Implementing a Branch Presence Predictor (BPP) that receives instruction addresses and predicts branch instructions during instruction fetching, allowing the BTB to catch up with instruction delivery and using accurate predictions from the BTB instead of less accurate alternatives, thereby eliminating the need for re-steering instruction fetching and branch prediction logic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If lookahead branch prediction is implemented with BTB searching in parallel with instruction fetching, then instruction pre-fetching efficiency is improved, but branch prediction latency increases when BTB falls behind the instruction stream

Engineering Contradiction:
Improveinstruction pre-fetching efficiencyVSAvoidbranch prediction latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements a branch pre-detection mechanism that operates in parallel with instruction fetching to identify branch instructions before the BTB needs to predict them. This preliminary detection allows the system to prepare for upcoming branches, ensuring the BTB can provide accurate predictions without falling behind the instruction stream, thus resolving the latency issue while maintaining pre-fetching efficiency

Inventive Principle:
Principle #10Preliminary action

2Reliability

If hierarchical predictors with two level caching are implemented, then prediction accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveprediction accuracyVSAvoidpredictor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the branch prediction function into two independent components: a simple branch pre-detection mechanism that identifies branch instructions, and the existing BTB that provides accurate predictions. This segmentation avoids the complexity of hierarchical predictors while maintaining accuracy, as each component performs its specific function without requiring complex integration between multiple prediction levels

Inventive Principle:
Principle #1Segmentation

3Reliability

If BTB footprint is made larger to improve prediction coverage, then prediction accuracy is improved, but instruction cache performance deteriorates

Engineering Contradiction:
Improveprediction coverageVSAvoidinstruction cache performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent introduces a branch pre-detection mechanism as an intermediary between instruction fetching and BTB searching. This intermediary identifies branch instructions early in the fetch process, allowing the system to optimize BTB search timing and reduce conflicts with instruction cache operations, thereby maintaining both prediction coverage and cache performance

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8874885B2Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs
Publication Date: 2014.10.28 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8874885B2 patent drawing
  • US8874885B2 patent drawing
  • US8874885B2 patent drawing

AI summary

Embodiments relate to mitigation of lookahead branch predication latency. An aspect includes receiving an instruction address in an instruction cache for fetching instructions in a microprocessor pipeline. Another aspect includes receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline. Another aspect includes determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor. Another aspect includes, based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction. Another aspect includes, based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline.