Branch Program Counter Array for Control Transfer Instructions
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Solution Overview
Problem
In multi-threaded processors, maintaining the value of the program counter (PC) for control transfer instructions (CTIs) to determine the actual direction and target is resource-intensive, leading to increased area and power consumption due to the need for additional circuitry to store and manage multiple thread states.
Innovation Solution
A Branch Program Counter Array (BPCA) is used to store program counter values corresponding to CTIs, allowing the execution unit to retrieve and verify the actual outcome of CTIs, thereby minimizing the impact on area and power consumption by avoiding the need for multi-ported storage cells and optimizing the storage of PC values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuitry is added to store and manage multiple thread states for CTIs, then prediction accuracy is improved, but area and power consumption increase
Solution Approach 1:
The program counter storage is segmented into multiple sectors, each containing multiple entries. This segmentation allows the system to store PC values for multiple threads efficiently without requiring a single large multi-ported storage structure, thereby reducing area while maintaining the ability to track multiple thread states for accurate prediction.
Solution Approach 2:
The BPCA structure serves multiple functions: it stores PC values for multiple threads, enables prediction of CTI outcomes, and allows verification of actual outcomes. By making the storage structure multi-functional, the patent avoids needing separate dedicated circuits for each function, thus reducing overall area while improving prediction accuracy.
2Measurement precision
If additional circuitry is added to store and manage multiple thread states for CTIs, then prediction accuracy is improved, but power consumption increases
Solution Approach 1:
By dividing the storage into sectors and entries, the system can selectively activate and manage only the necessary storage locations for active threads, reducing the overall power consumption compared to a fully associative multi-ported storage structure that would require continuous monitoring and management of all possible thread states.
Solution Approach 2:
The system manages PC value storage by allocating entries when needed and allowing them to be reused when no longer required. This dynamic allocation and recovery mechanism ensures that power is consumed only when actually storing and managing thread states, rather than continuously powering dedicated storage circuits for all possible threads.
3Speed
If a multi-ported storage cell is used to store PC values, then retrieval speed is improved, but area and complexity increase
Solution Approach 1:
The storage structure is divided into sectors with multiple entries each, allowing parallel access to different sectors without requiring multi-ported storage cells within each sector. This segmentation enables efficient retrieval by distributing access across multiple simpler storage locations rather than requiring complex multi-ported cells, thus reducing area while maintaining retrieval speed.
Solution Approach 2:
The patent organizes storage in a two-dimensional structure (sectors × entries) rather than using a single-dimensional multi-ported cell approach. This dimensional change allows the system to achieve parallel access capabilities through the sector-entry hierarchy without requiring each storage cell to have multiple ports, thereby reducing cell complexity and area while maintaining retrieval performance.
Data Source
AI summary
A system that for storing program counter values is disclosed. The system may include a program counter, a first memory including a plurality of sectors, a first circuit configured to retrieve a program instruction from a location in memory dependent upon a value of the program counter, send the value of the program counter to an array for storage and determination a predicted outcome of the program instruction in response to a determination that execution of the program instruction changes a program flow. The second circuit may be configured to retrieve the value of the program counter from a given entry in a particular sector of the array, and determine an actual outcome of the program instruction dependent upon the retrieved value of the program counter.