Branch Target Address Generation Using Physical Subset Embedding
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Solution Overview
Problem
Current semiconductor chips face data corruption and erroneous operations due to virtual-to-physical aliasing when generating branch target addresses, which occurs when multiple virtual addresses map to the same physical address, leading to incorrect instruction fetching and processing.
Innovation Solution
The semiconductor chip predecodes control flow instructions with a program counter relative displacement, replacing a portion of it with an untranslated physical subset of the target address, ensuring only the physical portion is embedded in the instruction cache, preventing aliasing by generating the full target address after fetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the full target address is generated during predecoding and stored in the instruction cache, then the target address is available earlier for next fetch prediction, but virtual-to-physical aliasing occurs when multiple virtual addresses map to the same physical address causing data corruption
Solution Approach 1:
The patent segments the target address into two parts: the upper bits (virtual address portion) and the lower bits (physical address portion). During predecoding, only the lower physical bits are generated and stored in the instruction cache, while the upper virtual bits are obtained later during instruction decoding. This segmentation allows early availability of the physical portion for prediction while avoiding aliasing conflicts that would occur with full virtual address storage.
2Productivity
If the full target address is stored in the instruction cache during predecoding, then fetch efficiency is improved, but aliasing causes incorrect instruction fetching
Solution Approach 1:
The target address is divided into virtual and physical portions. The instruction cache stores only the physical portion (lower bits) during predecoding, enabling efficient cache lookup without aliasing. The virtual portion (upper bits) is appended during the decode stage after the virtual address is available, ensuring the complete correct target address is formed without contamination from aliasing.
3Device complexity
If virtual addresses are used in the instruction cache, then address translation is simplified, but aliasing occurs when two virtual addresses map to the same physical address
Solution Approach 1:
The address translation process is segmented into two stages: predecoding and decoding. During predecoding, only the physical portion of the address is generated and stored, avoiding the need to store full virtual addresses that could alias. During decoding, the virtual address portion is obtained from the original instruction and combined with the pre-generated physical portion, achieving both simplicity in cache storage and uniqueness in final address formation.
Data Source
AI summary
A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.