Branch Target Storage for Out-of-Order Processor Performance
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Solution Overview
Problem
Modern superscalar microprocessors face performance losses due to stalls caused by control transfer instructions, as the instructions following a control transfer are not known until the transfer is executed, and branch prediction inaccuracies lead to speculative instruction fetching and execution, resulting in inefficiencies in multi-threaded processors.
Innovation Solution
A processor mechanism using a branch target array (BTA) to store predicted target addresses for control transfer instructions, where a tag associated with the control transfer instruction is used to retrieve the predicted target address, allowing efficient storage and transfer of predicted targets, even when instructions from different threads are interleaved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complete target addresses are passed through the pipeline for each control transfer instruction, then branch target accuracy is maintained, but processor performance deteriorates due to increased data transfer overhead and pipeline congestion
Solution Approach 1:
The patent segments the complete target address into two parts: a tag (identifying the control transfer instruction) and the full target address. Only the compact tag is passed through the pipeline with the instruction, while the complete target address is stored in a separate branch target address storage structure. This segmentation reduces data transfer overhead while preserving complete address information when needed.
Solution Approach 2:
The patent introduces a branch target address storage structure as an intermediary between the instruction fetch unit and the branch execution unit. This storage structure holds the complete target addresses indexed by tags, allowing the system to retrieve full addresses on demand without continuously transmitting them through the pipeline, thus acting as a mediator that decouples information storage from information transmission.
2Productivity
If branch prediction is implemented to speculatively fetch instructions beyond control transfer instructions, then processor throughput is improved, but performance deteriorates when mispredictions occur requiring instruction flushes
Solution Approach 1:
The patent implements preliminary branch target address prediction and storage before instruction execution. The branch prediction unit predicts target addresses and stores them in the branch target address storage structure indexed by tags. This allows the instruction fetch unit to speculatively fetch instructions from predicted targets in advance, improving throughput while maintaining the ability to quickly correct mispredictions by comparing predicted tags with actual execution results.
3Reliability
If separate branch target storage is allocated for each thread in multi-threaded processors, then thread-specific branch prediction accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal branch target address storage structure that serves multiple threads simultaneously. The storage structure is indexed by tags that are unique across all threads, allowing a single shared storage structure to hold branch target addresses for multiple threads without requiring separate storage for each thread. This reduces device complexity while maintaining thread-specific prediction accuracy through unique tag identification.
Data Source
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AI summary
A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support storage of predicted targets for multiple threads. In some embodiments, a CTI branch target may be stored by one element of a processor and a tag may indicate the location of the stored target. The tag may be associated with the CTI rather than associating the complete target address with the CTI. When the CTI reaches an execution stage of the processor, the tag may be used to retrieve the predicted target address. In some embodiments using a tag to retrieve a predicted target, CTI instructions from different processor threads may be interleaved without affecting retrieval of predicted targets.