Branch Target Buffer Locking Mechanism for Thrashing Reduction

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Solution Overview

Problem

In embedded processing systems, a small branch target buffer often results in thrashing, rendering it ineffective when the number of branches is large and executed only once, leading to zero usefulness due to constant replacement of contents.

Innovation Solution

Implementing a mechanism to lock a specified number or percentage of entries in the branch target buffer, allowing a subset of unique taken branches to remain locked, while allowing the remaining portion to be replaceable, thereby preventing constant thrashing and providing some performance advantage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the branch target buffer size is reduced to save area, then area is optimized, but the buffer becomes ineffective due to constant thrashing when handling large numbers of one-time branches

Engineering Contradiction:
Improvebranch target buffer areaVSAvoidbuffer effectiveness
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent segments the branch target buffer into two distinct parts: a locked portion and a replaceable portion. The locked portion retains entries for one-time branches that have already been executed, preventing them from being overwritten, while the replaceable portion handles new branch entries. This segmentation allows the buffer to maintain effectiveness for both recurring and one-time branches simultaneously, resolving the contradiction between small size and effectiveness.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If the branch target buffer is made small to optimize area, then area is saved, but performance advantage is lost due to zero usefulness from constant thrashing

Engineering Contradiction:
Improvebranch target buffer areaVSAvoidbranch execution performance
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

By dividing the buffer into locked and replaceable portions, the patent enables the locked portion to preserve performance-critical one-time branch entries while the replaceable portion accommodates new branches. This segmentation ensures that even with a small overall buffer size, the performance advantage is maintained by preventing thrashing of important entries.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-locking buffer entries before they are needed again. When a branch is executed, its entry is locked in advance to prevent subsequent overwrites, ensuring that the entry remains available for potential reuse without requiring a larger buffer to accommodate all possible branches.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If all buffer entries are replaceable to maximize adaptability, then new branches can be handled, but one-time branches cause constant thrashing and reduce buffer usefulness

Engineering Contradiction:
Improvebuffer adaptability to new branchesVSAvoidbuffer usefulness for one-time branches
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent resolves this contradiction by segmenting the buffer into a locked portion that protects one-time branch entries from being overwritten, and a replaceable portion that maintains adaptability to new branches. This segmentation allows the buffer to simultaneously preserve reliability for one-time branches while maintaining adaptability for new branch handling.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9311099B2Systems and methods for locking branch target buffer entries
Publication Date: 2016.04.12 NXP USA INC
  • US9311099B2 patent drawing
  • US9311099B2 patent drawing
  • US9311099B2 patent drawing

AI summary

A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.