Branch Target Buffer for Accurate Instruction Prefetching
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Solution Overview
Problem
Prefetching in processing systems faces inefficiencies due to the need for additional cache tag lookups when predicting branch target addresses, which consume power and time, especially when the target address is not in sequence with the branch instruction address.
Innovation Solution
Implementing a branch target address calculator that provides a second cache line to a second cache when the target address for a branch instruction is included in that cache line, even if it's not resident, and using a separate structure like a Branch Target Buffer (BTB) to store branch information, including target addresses, to accelerate prefetching by predicting branch targets and determining residency in the L1-I cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the prefetcher uses traditional sequential address prediction, then the prefetching process is simple, but the prefetching accuracy deteriorates when branch instructions are encountered
Solution Approach 1:
The patent introduces a Branch Target Buffer (BTB) as an intermediary structure between the branch instruction and the prefetcher. The BTB stores pre-calculated target addresses for branch instructions, allowing the prefetcher to accurately predict branch targets without implementing complex branch prediction logic directly in the prefetching path. This mediator structure enables accurate branch target prefetching while keeping the prefetcher itself relatively simple.
2Measurement precision
If the prefetcher starts a new stream for branch target addresses, then the prefetching accuracy improves, but the power consumption increases due to additional cache tag lookups
Solution Approach 1:
The patent performs branch target address calculation and BTB population in advance, before the actual prefetching operation. By pre-computing target addresses and storing them in the BTB when branch instructions are encountered during normal execution, the system avoids performing costly cache tag lookups at prefetch time. This preliminary action eliminates the need for additional power-consuming lookups during the prefetching phase while maintaining high prefetching accuracy.
3Measurement precision
If the prefetcher performs cache tag lookups to determine residency, then the prefetching accuracy improves, but the time consumption increases
Solution Approach 1:
The patent maintains a copy of branch target address information in the BTB structure that includes residency status. Instead of performing cache tag lookups to determine whether branch target addresses are resident in the L1-I cache, the system uses the pre-stored residency information in the BTB. This copying of residency status information eliminates time-consuming cache tag lookups while maintaining accurate knowledge of cache residency for prefetching decisions.
Data Source
AI summary
The present application describes a method and apparatus for prefetching instructions based on predicted branch target addresses. Some embodiments of the method include providing a second cache line to a second cache when a target address for a branch instruction in a first cache line of a first cache is included in the second cache line of the first cache and when the second cache line is not resident in the second cache.