Branch Target Buffer Prefetching for Server Workloads
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Solution Overview
Problem
Current processor technologies face challenges in managing large instruction footprints and deep software stacks, leading to frequent cache misses and branch target buffer (BTB) misses, which result in processing delays and pipeline flushes, especially in server workloads, due to limited cache capacity and BTB size.
Innovation Solution
The proposed solution involves a data processing apparatus with a branch prediction unit, a BTB, a BTB prefetch buffer, and a fetch target queue that uses branch-predictor-directed prefetching to fill both the instruction cache and BTB, distinguishing between genuine BTB misses and non-branch instructions, and prioritizing BTB miss probes to resolve misses efficiently without requiring significant metadata storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BTB size is increased to capture more branch targets, then the BTB miss rate decreases, but the chip area and metadata storage requirements increase significantly
Solution Approach 1:
The patent divides the BTB into two hierarchical levels: a small first-level BTB for frequently accessed branch targets and a larger second-level BTB for less frequently accessed targets. This segmentation allows the system to achieve low miss rates without requiring a single large BTB, thus reducing overall chip area while maintaining reliability.
Solution Approach 2:
The patent implements a branch target buffer refill mechanism that proactively loads branch target information into the BTB before it is needed. The refill unit monitors branch instruction patterns and pre-loads target addresses, reducing the likelihood of BTB misses without requiring larger buffer capacity.
2Loss of time
If prefetching is implemented to reduce cache misses, then memory latency is alleviated, but the complexity of the prefetcher increases and more metadata is required
Solution Approach 1:
The patent makes the branch predictor serve dual functions: it not only predicts branch outcomes for pipeline control but also drives instruction prefetching. The branch predictor's existing metadata structures are reused to identify prefetch targets, eliminating the need for separate prefetcher metadata and reducing overall system complexity while maintaining low memory latency.
Solution Approach 2:
The system uses its own branch prediction machinery to generate prefetch requests without requiring an external or separate prefetching unit. The branch predictor automatically identifies instructions that will be needed and triggers their prefetching, allowing the system to service its own prefetching needs using existing components.
3Use of energy by moving object
If a simple prefetcher is used, then the energy and chip area penalties are low, but the coverage and accuracy of prefetching are limited
Solution Approach 1:
The branch predictor is configured to serve both branch outcome prediction and instruction prefetching functions. By reusing the branch predictor's metadata structures and prediction logic, the system achieves high prefetch coverage and accuracy without adding dedicated prefetcher hardware, thus avoiding the energy and area penalties associated with simple prefetchers while maintaining high reliability.
Data Source
AI summary
A data processing apparatus is provided having branch prediction circuitry, the branch prediction circuitry having a Branch Target Buffer, BTB. A fetch target queue receives entries corresponding to a sequence of instruction addresses, at least one of the sequence having been predicted using the branch prediction circuitry. A fetch engine is provided to fetch instruction addresses taken from a top of the fetch target queue whilst a prefetch engine sends a prefetch probe to an instruction cache. The BTB is to detect a BTB miss when attempting to populate a storage slot of the fetch target queue and the BTB triggers issuance of a BTB miss probe to the memory to fetch at least one instruction from the memory to resolve the BTB miss using branch-prediction based prefetching.