Branch Target Cache Access Ahead of Instruction Fetch
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Solution Overview
Problem
Existing data processing systems face inefficiencies due to latency in branch prediction, leading to increased power consumption and instruction fetch latency, particularly when dealing with multiple branches and two-cycle latency in accessing branch target caches (BTACs) and instruction caches.
Innovation Solution
A data processing apparatus with a branch target cache and a data store that decouples BTAC logic from memory logic, allowing advanced BTAC accesses to reduce unnecessary cache accesses and fetch latency by storing and retrieving branch prediction information efficiently, using two program counters and a split data store to manage instruction flow and prediction data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If BTAC is accessed in parallel with instruction cache using two program counters, then branch prediction accuracy is improved, but fetch latency increases due to two-cycle latency in BTAC access
Solution Approach 1:
The patent performs BTAC accesses in advance of instruction cache accesses by using two program counters (PC1 for BTAC, PC2 for instruction cache). PC1 is incremented by 2 while PC2 is incremented by 1, allowing the branch target cache to be queried ahead of time so that branch prediction results are ready before the actual instruction fetch completes, eliminating the two-cycle latency penalty.
Solution Approach 2:
The patent introduces an intermediate buffer that stores branch prediction results from the BTAC before they are needed by the instruction fetch pipeline. This buffer acts as a mediator that decouples the BTAC access timing from the instruction cache access timing, allowing the two operations to proceed at different rates without blocking each other.
2Productivity
If buffers are used to store fetched instructions and branch predictions, then pipeline bubbles are hidden, but device complexity increases
Solution Approach 1:
The patent segments the buffer structure into multiple independent buffers, each handling specific stages of the instruction fetch pipeline. Instead of one large complex buffer, the system uses several smaller buffers (such as a first buffer for branch predictions and a second buffer for fetched instructions) that can be managed independently, reducing overall complexity while maintaining continuous instruction flow.
3Loss of energy
If BTAC access is performed two cycles in advance, then unnecessary cache accesses are reduced, but instruction fetch latency increases due to waiting for instruction return
Solution Approach 1:
The patent performs BTAC accesses two cycles in advance of instruction cache accesses, allowing branch prediction to be completed before the actual instruction fetch. This preliminary action identifies which instructions will be needed, enabling the system to avoid fetching instructions that won't be executed, thereby reducing power consumption without significantly impacting overall fetch latency.
Solution Approach 2:
The system uses the branch prediction information to self-regulate the instruction fetch process. When a branch is predicted to be taken, the fetch unit automatically adjusts to fetch from the branch target address instead of the sequential next instruction, eliminating the need for subsequent fetch corrections and reducing unnecessary memory access power consumption.
4Speed
If more instructions are accessed in BTAC than prefetched from memory, then advance in instruction stream is achieved, but data store complexity increases
Solution Approach 1:
The data store is segmented into multiple fields or entries, each corresponding to specific instruction addresses or branch targets. Instead of a single large associative memory, the system divides the storage into manageable segments that can be independently accessed and managed, reducing the complexity of the overall data store while maintaining the ability to advance the instruction stream efficiently.
Solution Approach 2:
The patent introduces a second program counter dimension (PC1 for BTAC, PC2 for instruction cache) to manage the data store accesses. This additional dimensional approach allows the system to track and access branch prediction data independently from the main instruction fetch sequence, enabling faster instruction stream advancement without proportionally increasing data store complexity.
Data Source
AI summary
A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instruction; and said data processing apparatus is operable over a period of time to access predetermined information corresponding to more instructions within said branch target cache than instructions it prefetches from said memory such that said accesses to said branch target cache develop an advance in said instruction stream with respect to accesses to said memory; and said prefetch unit is operable to access said data store and to determine if there is data corresponding to an instruction within said data store that indicates that said instruction specifies a branch operation that will be taken and will cause a change in instruction flow.