Branch Target Cache Return Address Prediction Circuit
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Solution Overview
Problem
Existing branch prediction circuits face difficulties in accurately predicting return instructions due to varying return addresses resulting from multiple call instructions, leading to performance bottlenecks and increased cycle waste in determining target addresses.
Innovation Solution
A system comprising a branch target cache, a memory for storing return target stacks, and a circuit that determines prediction values for return instructions, selects return addresses, and manages hits or misses in the branch target cache to optimize return address selection, using prediction tables and Bloom filters to improve prediction accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If branch prediction circuits track return addresses using traditional methods, then call instructions with fixed targets can be predicted accurately, but return instructions with varying targets cannot be predicted accurately
Solution Approach 1:
The system segments the return address tracking by separating call instructions from return instructions and organizing them in separate stacks. Call addresses are pushed onto a call stack when call instructions are detected, and return addresses are pushed onto a return stack when return instructions are detected. This segmentation allows independent tracking of each instruction type, enabling accurate prediction despite varying targets.
Solution Approach 2:
The system performs preliminary action by pre-calculating and storing return addresses in the return target stack before they are needed for prediction. When a call instruction is executed, its return address is computed and stored in advance. When the corresponding return instruction is encountered, the pre-stored address is immediately available for prediction, eliminating the need to recalculate or search for the target address at prediction time.
2Speed
If the system stores return addresses in a stack structure, then return address retrieval is fast, but memory usage increases
Solution Approach 1:
The system extracts only the essential information needed for return address prediction and stores it in compact stack structures. Instead of storing complete instruction contexts or complex data structures, only the critical return addresses are extracted and stored in the return target stack. This selective extraction minimizes memory consumption while maintaining fast retrieval capability through the stack's LIFO structure.
3Measurement precision
If the system uses prediction tables and Bloom filters, then prediction accuracy improves, but circuit complexity increases
Solution Approach 1:
The system introduces prediction tables and Bloom filters as intermediary structures between the return target stack and the branch prediction logic. These intermediaries enable efficient lookup and verification of return addresses without requiring complex direct comparison logic. The Bloom filter provides a space-efficient probabilistic data structure for verifying address membership, while prediction tables store pre-computed address mappings, together reducing overall circuit complexity despite adding intermediate components.
Data Source
AI summary
An apparatus includes a branch target cache configured to store one or more branch addresses, a memory configured to store a return target stack, and a circuit. The circuit may be configured to determine, for a group of one or more fetched instructions, a prediction value indicative of whether the group includes a return instruction. In response to the prediction value indicating that the group includes a return instruction, the circuit may be further configured to select a return address from the return target stack. The circuit may also be configured to determine a hit or miss indication in the branch target cache for the group, and to, in response to receiving a miss indication from the branch target cache, select the return address as a target address for the return instruction.