Branch Target Prediction for Polymorphic Branch Latency
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Solution Overview
Problem
Existing branch prediction techniques face significant latency in predicting the target address of certain branch instructions, particularly polymorphic branches, which can limit performance gains and introduce pipeline bubbles and increased power consumption.
Innovation Solution
Implement default prediction circuitry for quick target address prediction, supplemented by further prediction circuitry for accurate predictions, and utilize monitoring circuitry to update the default prediction only when an update condition is met based on observed target addresses over multiple occurrences, reducing unnecessary updates and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If further prediction circuitry is used to improve prediction accuracy, then prediction accuracy is improved, but latency increases
Solution Approach 1:
The prediction circuitry is segmented into two independent parts: default prediction circuitry that operates immediately without waiting for accurate prediction, and further prediction circuitry that provides improved accuracy but with latency. This segmentation allows the system to use the fast default prediction while the more accurate prediction is computed in parallel, resolving the contradiction between speed and accuracy.
Solution Approach 2:
The default prediction circuitry acts as an intermediary that provides immediate prediction results while the further prediction circuitry refines the accuracy. The default prediction serves as a mediator between the immediate performance requirement and the accuracy requirement, allowing both to be satisfied at different levels.
2Measurement precision
If default prediction circuitry is updated frequently to improve accuracy, then prediction accuracy is improved, but power consumption increases
Solution Approach 1:
The monitoring circuitry provides feedback about the actual target addresses observed from branch instructions. This feedback is used to determine when updates to the default prediction circuitry are beneficial, creating a closed-loop system that adjusts prediction accuracy dynamically based on actual performance data, thereby reducing unnecessary updates and power consumption.
Solution Approach 2:
The system changes the parameter of prediction accuracy dynamically by updating the default prediction circuitry only when monitoring data indicates improvement is needed. This parameter change is conditional and data-driven, allowing the system to optimize between accuracy and power consumption based on actual branch instruction patterns.
3Measurement precision
If default prediction circuitry is updated continuously, then prediction accuracy is improved, but device complexity increases
Solution Approach 1:
The monitoring circuitry automatically monitors branch instruction execution and determines when updates to the default prediction circuitry are beneficial. This self-service mechanism eliminates the need for complex external control logic, as the system self-regulates its own updating based on observed performance data.
Solution Approach 2:
The update decision logic is extracted into a separate monitoring circuitry component that independently analyzes branch instruction patterns. This extraction simplifies the overall system architecture by separating the monitoring function from the prediction function, making each component more manageable and easier to implement.
Data Source
AI summary
An apparatus, and corresponding method, is provided, the apparatus comprising default prediction circuitry, responsive to an address associated with a given branch instruction, to generate a default prediction of a target address for the given branch instruction, and further prediction circuitry arranged, when the given branch instruction is a given type of branch instruction, to generate a further prediction of the target address for the given branch instruction. The further prediction is generated later than the default prediction and is used in place of the default prediction in the event that the further prediction differs from the default prediction. Monitoring circuitry is arranged, responsive to detecting an update condition based on monitoring an observed indication of the target address for multiple occurrences of the given branch instruction, to cause the default prediction circuitry to be updated so as to alter the default prediction generated by the default prediction circuitry for the given branch instruction.