Branch Tracing Mechanism for Microprocessor Predicated Instructions
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Solution Overview
Problem
Advanced microprocessors with predicated and expanded instructions complicate burn-in operations and program evaluation, making it difficult to detect and correct programming errors due to unpredictable instruction execution and cascaded sub-instruction execution, which hinders effective branch tracing.
Innovation Solution
A branch tracing mechanism that includes signal processing for predicated and expanded instructions, using a state machine to control multiplexers and a FIFO memory to store address pairs, allowing clear tracking of program counter branches and sub-instruction execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If predicated instructions are used in microprocessors, then processing capability is improved, but branch tracing accuracy deteriorates because predicated instructions may not be executed
Solution Approach 1:
The patent introduces a branch trace device as an intermediary component between the microprocessor and the analysis tool. This device includes a program counter to capture instruction addresses and a trace memory to store branch trace information. The device selectively captures and records branch information, serving as a mediator that translates complex predicated instruction execution into understandable trace data, thereby resolving the contradiction between improved processing capability and maintained tracing accuracy.
2Productivity
If expanded instructions are used in microprocessors, then processing capability is improved, but branch tracing complexity increases due to cascaded sub-instruction execution
Solution Approach 1:
The patent segments the branch tracing function into distinct components: a program counter for capturing instruction addresses, a trace memory for storing branch information, and control logic for selective recording. This segmentation allows the system to handle expanded instructions with cascaded sub-instructions by capturing only the relevant branch points, thereby reducing tracing complexity while maintaining the ability to process complex instruction sets.
3Ease of operation
If typical branch tracing mechanisms are used, then simplicity is maintained, but error detection capability deteriorates for advanced instructions
Solution Approach 1:
The patent implements preliminary action by pre-configuring the branch trace device with program counter and trace memory structures that are specifically designed to handle both standard and advanced instructions. The device proactively captures branch information at the source before execution, preparing the trace data in advance. This preliminary preparation enables simple operation of the tracing mechanism while simultaneously improving error detection capability for predicated and expanded instructions.
Data Source
AI summary
A device generates an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type. The device includes: a first block to receive a first signal representative of an actually executed instruction; a second block to receive a second signal representative of an expanded instruction; a third block to receive a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by the microcontroller, microprocessor or data processing unit; at least one register to store consecutive addresses pointed to by a program counter; a fourth block to process the first, second and third signals in order to determine a pair having a source address and a destination address for an address branch, when appropriate; and a storage unit to store said address pair.