Branched Thin-Film Transistor Layout for Heat Dissipation Reliability

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Solution Overview

Problem

The source and drain branches of thin film transistors in existing display devices are arranged in a high concentration, leading to heat concentration and poor reliability of the display devices.

Innovation Solution

A thin film transistor design where the source and drain electrode branches are divided into multiple cells, each cell comprising multiple source, drain, and semiconductor branches, arranged in a multi-wiring design to improve heat dissipation and reduce heat generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the source and drain branches are arranged in high concentration to increase charging current, then the charging current of the TFT is improved, but heat concentration occurs leading to poor reliability

Engineering Contradiction:
Improvecharging currentVSAvoiddevice reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The source electrode is divided into multiple source electrode branches (first source electrode branch, second source electrode branch, etc.) and the drain electrode is divided into multiple drain electrode branches (first drain electrode branch, second drain electrode branch, etc.). These branches are spatially separated and arranged in a distributed manner rather than concentrated, allowing the charging current to be distributed across multiple paths. This segmentation reduces current density in each branch and disperses heat generation, solving the heat concentration problem while maintaining sufficient total charging current for high mobility oxide TFTs.

Inventive Principle:
Principle #1Segmentation

2Power

If the width to length ratio of the TFT channel is increased to increase charging current, then the charging current is improved, but the device area increases

Engineering Contradiction:
Improvecharging currentVSAvoidTFT area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

Instead of increasing the width-to-length ratio in the traditional planar configuration, the patent introduces a multi-dimensional electrode branch structure. Multiple source and drain branches are arranged in a spatial distribution pattern, effectively utilizing the vertical and lateral dimensions to create parallel current paths. This dimensional approach increases the effective channel area for current flow without proportionally increasing the overall device footprint, achieving high charging current in a compact area suitable for non-display regions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Temperature

If multiple source and drain electrode branches are distributed to improve heat dissipation, then heat dissipation is improved, but the device complexity increases

Engineering Contradiction:
Improveheat dissipationVSAvoidelectrode structure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent combines multiple source electrode branches into a unified source electrode structure and multiple drain electrode branches into a unified drain electrode structure. The branches are electrically connected in parallel between their respective terminals, creating a merged structure that functions as a single electrode while providing distributed heat dissipation. This merging approach maintains structural integrity and simplifies fabrication compared to completely separate electrodes, reducing device complexity while achieving improved thermal management.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12230683B2Thin film transistor having a semiconductor layer comprising a plurality of semiconductor branches
Publication Date: 2025.02.18 BOE TECHNOLOGY GROUP CO LTD
  • US12230683B2 patent drawing
  • US12230683B2 patent drawing
  • US12230683B2 patent drawing

AI summary

The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor including a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer including a plurality of semiconductor branches; a plurality of source electrode branches. The plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.