Branching Memory-Bus Module Reducing Latency
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Solution Overview
Problem
The serial chain topology used by fully-buffered memory modules results in increased delays for data transmission between memory modules and the host CPU, especially in larger memory systems, due to the limited number of ports in current Advanced Memory Buffers (AMBs) which leads to longer signal paths and higher latency.
Innovation Solution
Introducing a branching AMB with multiple downlink ports and a single uplink port, allowing for the creation of branches in the memory bus topology, reducing the number of intervening modules and thus minimizing delays by distributing data through point-to-point links between modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a serial chain topology is used with limited AMB ports, then device complexity is reduced and compatibility with standard modules is maintained, but data transmission delay increases and productivity decreases
Solution Approach 1:
The patent segments the memory bus topology by introducing a branching AMB that divides the serial chain into multiple parallel branches. Each branch connects to standard fully-buffered memory modules, allowing data to travel through shorter paths and reducing overall transmission delay while maintaining compatibility with existing modules.
Solution Approach 2:
The patent transitions from a one-dimensional serial chain topology to a two-dimensional branching topology. The branching AMB creates multiple downlink ports that form parallel pathways, effectively adding a dimensional aspect to the previously linear data transmission path, thereby reducing delays without increasing complexity.
2Productivity
If multiple downlink ports are added to AMB to create branches, then data transmission speed improves and delay reduces, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The branching AMB is designed with multiple downlink ports that can connect to standard fully-buffered memory modules, making it universally compatible with existing module standards. This multi-functionality allows a single AMB design to serve both as a traditional single-port buffer and as a branching node, simplifying manufacturing by reusing proven components and interfaces.
Solution Approach 2:
The patent uses copying by replicating the standard fully-buffered memory module interface multiple times in the branching AMB. Each downlink port copies the standard interface specifications, allowing identical module designs to be used across all branches. This copying approach simplifies manufacturing by maintaining consistency with existing production processes.
3Loss of time
If branches are introduced in memory bus topology, then signal path length decreases and transmission delay reduces, but signal distortion and interference may increase
Solution Approach 1:
The branching AMB acts as an intermediary device that actively manages signal distribution across multiple branches. It includes signal buffering, retiming, and regeneration capabilities that compensate for potential signal distortion introduced by the branching topology. The AMB re-times and re-conditions signals before forwarding them to each branch, maintaining signal integrity while enabling shorter transmission paths.
Data Source
AI summary
A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.