Breakable Top Electrode Memory Cell for Failed-State Isolation
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Solution Overview
Problem
Memory devices with memory elements that fail over time result in wasted resources due to discarded rows and columns, and the short circuit state resistance variability complicates state identification, leading to performance and reliability issues.
Innovation Solution
A memory device with a breakable top electrode over a memory element, where a breakdown signal creates an open circuit with a higher voltage to isolate failed elements, reducing resistance variability and allowing functional elements to remain operational.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory elements are monitored for failure, then reliability is improved, but device complexity increases due to additional monitoring circuitry and control mechanisms
Solution Approach 1:
The memory element performs self-diagnosis by monitoring its own resistance characteristics. When failure is detected through resistance threshold comparison, the element automatically transitions to an open circuit state via the breakable electrode, isolating itself without requiring external intervention or complex monitoring circuitry.
Solution Approach 2:
The failed memory element is electrically extracted from the operational array by creating an open circuit through the breakable top electrode. This isolation removes the failed element from the conductive network, allowing the rest of the array to continue functioning while the failed element is effectively taken out of service.
2Reliability
If rows and columns are discarded when memory elements fail, then reliability is maintained, but productivity decreases due to loss of functional memory elements
Solution Approach 1:
The isolation mechanism is segmented to the individual memory element level rather than affecting entire rows or columns. The breakable top electrode creates a localized open circuit that confines the failure impact to a single cell, allowing other memory elements in the same row and column to remain fully operational.
Solution Approach 2:
The failure isolation property is applied locally at the specific failed memory element location. The open circuit state is created only at the failed element's top electrode, leaving the electrical characteristics of all other memory elements unchanged and fully functional.
3Measurement precision
If resistance thresholds are used to identify memory states, then measurement precision is achieved, but difficulty of detecting and measuring increases due to short circuit state resistance variability
Solution Approach 1:
Instead of trying to measure and interpret variable resistance values to detect failure, the approach is inverted: the system creates a definitive open circuit state that produces a unique, easily detectable electrical condition (infinite resistance). This transforms the detection problem from measuring variable resistance to detecting the presence or absence of conductivity.
Solution Approach 2:
The electrical state of the memory element undergoes a dramatic change analogous to color change - from conductive (low resistance) to non-conductive (open circuit). This binary transformation creates a clear, unambiguous signal that is easily distinguishable from the intermediate resistance states of operational memory elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The open circuit state provides a clear distinction between operational and failed states, minimizing waste and enhancing performance and reliability by maintaining functional elements in the same row and column.
Implementation Method 1
the top electrode configured to create an open circuit in the memory device
Implementation Method 2
A breakdown signal with a higher voltage than the read signal and the write signal causes the top electrode to break
Data Source
AI summary
The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.