Breakable Top Electrode Memory Cell for Failed Element Isolation
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Solution Overview
Problem
In memory devices, failed memory elements often lead to the discard of entire rows or columns, resulting in waste of functional elements due to variability in resistance states, particularly the short circuit state, which complicates identification and reduces performance and reliability.
Innovation Solution
A memory device with a breakable top electrode over a memory element is designed, where the top electrode is narrower than the memory element, allowing a breakdown signal to create an open circuit when a failure is detected, eliminating the failed element without affecting others in the same row or column, thereby reducing variability and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory element fails due to variability in resistance states, then the entire row or column must be discarded, but this results in waste of functional elements and reduces memory device productivity
Solution Approach 1:
The patent segments the memory element into three distinct resistance states (first state, second state, and short circuit state) rather than treating failures as binary. This segmentation allows the memory device to distinguish between functional elements with variable resistance and truly failed elements, enabling selective discarding of only the short circuit state elements while preserving functional elements in other states, thus improving effective yield without compromising reliability
Solution Approach 2:
The patent changes the parameter interpretation by redefining resistance state categories. Instead of treating resistance variability as a binary pass/fail condition, it establishes three parameter ranges: a first resistance range (first state), a second resistance range (second state), and a short circuit condition (short circuit state). This parameter transformation enables the memory device to identify and discard only elements in the short circuit state while maintaining functional elements, resolving the contradiction between reliable identification and productivity
2Reliability
If the top electrode is made narrower to enable selective breakdown, then the open circuit creation becomes more precise, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by making the top electrode narrower than the memory element only in the critical region where breakdown is needed. This localized dimensional variation enables precise open circuit creation at the electrode-memory element interface without requiring the entire top electrode structure to meet stringent dimensional tolerances, thus improving failed element isolation while managing manufacturing precision requirements
Solution Approach 2:
The patent incorporates the narrower top electrode design during the preliminary manufacturing stage, establishing the dimensional relationship between the top electrode and memory element before operation. This preliminary action ensures that the breakdown path is pre-configured to be more precise and localized, reducing the need for post-manufacturing adjustments and simplifying the overall manufacturing precision requirements while achieving reliable failed element isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively disregards failed memory elements by creating a stable open circuit with high resistance, minimizing waste and enhancing the performance and reliability of the memory device by eliminating the ambiguity in resistance states.
Implementation Method 1
allowing a breakdown signal to create an open circuit when a failure is detected
Data Source
AI summary
The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.