Breakdown Detection Circuit for Memory Cell Programming
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Solution Overview
Problem
The integration of floating gate memory and logic in CMOS technology for high-performance and low-power systems-on-chip is challenging due to the complexity and cost of integrating additional processing, leading to the increased use of one-time programmable (OTP) memory, which cannot detect defective cells during operation.
Innovation Solution
A breakdown detection circuit using three NMOS transistors, a flag bit cell design, and a worddrive circuit for biasing memory word-lines, allowing for the detection of abnormally high currents during programming and managing data in defective memory cells, enabling the identification and management of defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If OTP memory is programmed during device operation, then the device can function as intended, but defective cells cannot be detected or screened out
Solution Approach 1:
The patent implements a breakdown detection circuit that is activated during the programming process to detect defective cells before they can cause system failure. The detection circuit monitors for abnormal conditions (breakdown events) that occur when programming voltage is applied, allowing defective cells to be identified and marked as such during the programming operation itself, rather than requiring separate pre-shipment testing
Solution Approach 2:
The patent employs a feedback mechanism where the breakdown detection circuit continuously monitors the programming process and provides real-time information about cell integrity. When a defective cell is detected through abnormal current or voltage conditions during programming, the system receives feedback about the defect and can respond by marking the cell as defective, preventing future operations on that cell
2Reliability
If breakdown detection circuit is added to detect defective cells, then reliability improves, but device complexity increases
Solution Approach 1:
The patent introduces a breakdown detection circuit as an intermediary component that sits between the programming voltage source and the memory cells. This circuit includes voltage division elements and current monitoring components that detect breakdown events without requiring major restructuring of the memory array itself, thereby adding detection capability with minimal impact on the core memory structure
Solution Approach 2:
The breakdown detection functionality is implemented locally at strategic points in the circuit rather than requiring every memory cell to have full detection circuitry. The detection circuit monitors aggregate conditions and can identify defective cells through localized measurements, reducing the overall complexity compared to implementing full detection capability at each cell location
3Reliability
If monitoring impedance level is used to detect breakdown, then defective cells can be identified, but additional circuitry and power consumption increase
Solution Approach 1:
The breakdown detection circuit is designed to utilize the existing programming voltage and current paths to perform detection functions. The same voltage applied for programming also serves as the test voltage for detecting breakdown, and the programming current itself provides the signal for detection, eliminating the need for separate test voltage sources or additional power-consuming measurement circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the detection and management of defective memory cells, preventing data loss and protecting the system from further damage, while improving write speed and reducing the risk of data corruption in OTP memory systems.
Implementation Method 1
detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit
Implementation Method 2
the third transistor is arranged to sustain the programming voltage in case of breakdown
Data Source
AI summary
Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.