Breakpoint Circuitry Evaluating Conditions During Clock Oscillation
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Solution Overview
Problem
Debugging hardware accelerators is time-consuming due to the repeated stopping and restarting of the clock signal to evaluate breakpoints, which slows down the execution of the hardware accelerator.
Innovation Solution
A circuit arrangement comprising an execution circuit, a control circuit, and a debug circuit that evaluates operation-specific breakpoints without stopping the clock signal, allowing the execution circuit to continue operating while evaluating breakpoint conditions, and supports restarting the clock in a timing-safe manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock signal is stopped after each cycle to evaluate breakpoint conditions, then the breakpoint evaluation can be performed accurately, but the execution speed of the hardware accelerator is significantly reduced
Solution Approach 1:
The patent pre-loads breakpoint condition data into buffer memory before execution, and pre-configures the evaluation logic circuitry. This allows the breakpoint evaluation to proceed simultaneously with execution using pre-prepared data, eliminating the need to stop the clock for data preparation while maintaining accurate evaluation.
2Measurement precision
If the clock signal is stopped repeatedly to evaluate breakpoints, then the breakpoint conditions can be checked thoroughly, but the debugging process becomes extremely time-consuming
Solution Approach 1:
The patent implements continuous breakpoint evaluation by running the evaluation logic in parallel with the execution circuit. The clock signal continues to drive both the execution and the breakpoint evaluation simultaneously, eliminating repeated stop-start cycles while maintaining thorough condition checking through continuous monitoring of all breakpoint criteria.
Solution Approach 2:
The patent divides the breakpoint evaluation into separate logical components: condition registration, data buffering, parallel evaluation logic, and result latching. This segmentation allows each component to operate independently and simultaneously, enabling thorough evaluation without requiring sequential stop-start operations that waste time.
3Measurement precision
If the clock signal is stopped for each breakpoint evaluation, then the state of the hardware accelerator can be examined accurately, but the execution flow is significantly slowed down
Solution Approach 1:
The patent introduces buffer memory and latch circuits as intermediary elements between the execution circuit and the breakpoint evaluation logic. These intermediaries capture execution state data and make it available to the evaluation logic without requiring the execution to pause, allowing accurate state examination to proceed in parallel with execution.
Data Source
AI summary
An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.