Configurable Breakpoint Unit for Interrupt Service Routine Debugging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microcontrollers and microprocessors have limited breakpoint configuration capabilities, restricting flexible debugging due to limited silicon real estate and functionality, which hinders accurate debugging, especially in interrupt service routines.
Innovation Solution
A processor device with debug capabilities, including a central processing unit, interrupt controller, and a configurable breakpoint unit that can be set to activate only during interrupt service routines, allowing for advanced breakpoint configurations based on interrupt status, instruction addresses, and data access conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional breakpoint units are used in microcontrollers, then the device can be debugged with basic functionality, but the breakpoint configuration capability is limited due to restricted silicon real estate and functionality
Solution Approach 1:
The breakpoint unit is enhanced to perform multiple functions: it can detect instruction addresses, data access addresses, interrupt status, and combine these conditions through logical operations. This multi-functionality allows a single breakpoint unit to replace what would otherwise require multiple separate detection circuits, thereby improving adaptability without proportionally increasing silicon real estate.
Solution Approach 2:
The patent combines multiple detection functions (instruction address matching, data address matching, interrupt status detection) into a unified breakpoint unit. The condition register merges multiple condition bits (instruction match, data match, interrupt status) into a single configuration structure, allowing complex breakpoint conditions to be set and evaluated within a compact integrated circuit.
2Measurement precision
If basic breakpoint functionality is provided, then the device structure remains simple, but debugging accuracy is insufficient especially in interrupt service routines
Solution Approach 1:
The breakpoint unit incorporates specific detection mechanisms tailored for different debugging needs: instruction address detection for code debugging, data address detection for memory debugging, and interrupt status detection for interrupt handling debugging. Each detection mechanism is optimized for its specific purpose, providing high debugging accuracy for particular scenarios without requiring the entire system to be overly complex.
Solution Approach 2:
The breakpoint unit dynamically evaluates multiple conditions (instruction address match, data address match, interrupt status) and combines them through logical operations to determine whether to trigger a breakpoint. This dynamic condition evaluation allows the debug unit to adapt its behavior based on the current execution context, improving debugging accuracy for different scenarios including interrupt service routines.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.