Semiconductor Bridge Arch Packaging for Dense 3D Interconnects
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Solution Overview
Problem
Forming connections between substrates in semiconductor devices can cause complications, and existing packaging methods do not effectively address thermal, physical, and electrical protection of multiple computational components in integrated circuits.
Innovation Solution
A packaging architecture featuring bridge arches and redistribution layers is used to connect compute devices and device packages, with active connecting elements that include transistors and vias, forming a stack logic and memory building block architecture that provides efficient signal routing and power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If connections are formed between substrates to increase computation, then computational density is improved, but packaging complexity and difficulty of integration worsen
Solution Approach 1:
The packaging structure is divided into multiple layers (first layer, second layer) with distinct functional regions. Each layer contains specific components (compute devices, device packages, connecting elements) arranged in segmented fashion, allowing independent optimization of each segment while achieving high overall integration.
Solution Approach 2:
The patent transitions from two-dimensional substrate connections to three-dimensional stacked architecture. Compute devices are positioned between device packages in vertical stacking, with connecting elements routing signals through multiple layers. This dimensional change enables higher computational density without proportionally increasing packaging complexity.
2Productivity
If multiple computational components are integrated in a single unit, then computational capability is improved, but thermal protection and physical protection become more difficult
Solution Approach 1:
The integrated unit is segmented into spatially separated regions: compute devices in one area, device packages in another, with intermediate connecting elements. This segmentation creates natural thermal zones and physical protection barriers, allowing heat management and protection strategies to be applied to specific regions rather than the entire integrated unit.
Solution Approach 2:
Connecting elements serve as intermediary structures between compute devices and device packages. These intermediaries provide physical separation and protection, acting as buffer zones that can manage thermal stress and mechanical forces independently of the sensitive compute devices.
3Speed
If connecting elements with interface logic are used to connect compute devices to device packages, then signal routing efficiency is improved, but device complexity increases
Solution Approach 1:
Interface logic is merged directly into the connecting elements rather than being separate components. This integration consolidates routing and interface functions into unified structures, improving signal routing efficiency while avoiding the added complexity of discrete interface devices.
Solution Approach 2:
The connecting elements are designed with multi-functionality, serving both as physical interconnects and as interface logic units. This universal design allows the same structure to perform multiple functions (signal transmission, routing, and interface processing), reducing overall device complexity despite enhanced routing capabilities.
Data Source
AI summary
Disclosed herein are methods, systems and devices including a first layer with a first compute device, a first device package, and a second device package, with the first compute device between the first device package and the second device package. The device may include a second layer with a first connecting element and a second connecting element, the first connecting element electrically connecting the first compute device to the first device package, and the second connecting element electrically connecting the first compute device to the second device package.