Bridge-Arm Power Wafer Layout for Low-Inductance High-Frequency Switching
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Solution Overview
Problem
Existing power semiconductor wafers face challenges in reducing input loop inductance, improving current sharing performance, and enhancing reliability under high-frequency conditions, particularly due to inconsistent loop inductance and non-uniform current distribution in high-frequency switch processes.
Innovation Solution
A power semiconductor wafer design with a substrate featuring long-strip-shaped first and second switch areas arranged parallel to the long edge, a logic circuit area, and decoupling capacitors positioned along the long edge, forming a high-frequency bridge arm with synchronized current distribution and reduced loop inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the lower switch QL and upper switch QH are respectively concentrated in corresponding areas, then the layout is simple, but the input loop area is large and frequency is limited below 1 MHz
Solution Approach 1:
The patent divides the concentrated switch areas into multiple smaller unit areas. Specifically, the lower switch QL area is divided into multiple QL unit areas and the upper switch QH area is divided into multiple QH unit areas. These unit areas are arranged in an interleaved pattern to reduce the input loop area while maintaining manufacturing simplicity.
Solution Approach 2:
The patent transitions from a simple parallel arrangement to a two-dimensional interleaved layout pattern. The unit areas are arranged alternately in both horizontal and vertical directions, creating a more compact configuration that reduces the overall input loop area and enables higher operating frequencies.
2Speed
If the wafer is divided into a plurality of areas to reduce loop area, then the frequency can be increased to 1 MHz or above, but the high and low voltage boundary lines are numerous and wafer utilization rate is low
Solution Approach 1:
The patent merges adjacent unit areas of the same type (QL or QH) to form larger functional blocks where applicable. This reduces the number of discrete boundaries while maintaining the interleaved low-inductance structure. The merging strategy optimizes the balance between frequency performance and manufacturing complexity.
3Shape
If the input decoupling capacitor Cbus is arranged on the outer side along the partition arrangement direction, then the aspect ratio is reduced, but the input loop inductance varies and current distribution is non-uniform
Solution Approach 1:
The patent applies different arrangement strategies to different regions of the wafer. Unit areas closer to the edge have optimized capacitor connections, while internal unit areas follow the interleaved pattern. This local optimization ensures uniform current distribution across the entire wafer surface while maintaining good aspect ratio characteristics.
4Reliability
If the width of the short edge is reduced to improve current uniformity, then the aspect ratio becomes larger, but the yield is influenced
Solution Approach 1:
The patent optimizes the dimensional parameters of the unit areas and their spacing to achieve a balanced aspect ratio. By carefully controlling the width and length ratios of the interleaved patterns, the design achieves uniform current distribution without excessively increasing the overall aspect ratio, thereby maintaining good wafer yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved frequency performance, enhanced reliability, and reduced switching loss by optimizing the aspect ratio and uniform current distribution across the wafer, supporting frequencies up to 3 MHz or higher.
Implementation Method 1
an input loop comprises the input decoupling capacitor Cbus, the upper switch QH and the lower switch QL
Implementation Method 2
a voltage overshoot can be formed on the input loop inductor Lloop under high frequency due to V=Lloop*di/dt
Data Source
AI summary
The application discloses a power semiconductor wafer of a high-frequency bridge arm integrated with a single crystal wafer. The power semiconductor wafer comprises a substrate and a device structure area, wherein the device structure area comprises a first switch area, a second switch area and a logic circuit area; a DC+ electrode, a DC− electrode and an SW electrode are arranged on the power semiconductor wafer; and the first switch area and the second switch area comprise long-strip-shaped areas parallel to the long edge and are arranged in parallel. Another aspect of the present application further provides a power conversion module, comprising a bridge arm circuit, wherein the bridge arm circuit comprises an outer decoupling capacitor and a power semiconductor wafer, or comprises an outer decoupling capacitor, a laminated decoupling capacitor and a power semiconductor wafer.