Bridge-Bonded Die Stacks for Compact Semiconductor Packaging
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Solution Overview
Problem
Semiconductor package manufacturers face challenges in reducing the volume of semiconductor packages while increasing capacity and performance, due to limitations in interconnecting semiconductor dies and inefficiencies in space utilization.
Innovation Solution
The implementation of cross stack bridge bonding structures within semiconductor packages, which include a shingled and reverse-shingled die stack configuration with bridging chips and wire segments, allows for more efficient use of space and reduced connections between dies and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor dies are stacked vertically in a shingled arrangement with direct connections to the substrate, then capacity and performance increase, but manufacturing complexity and space utilization inefficiency worsen
Solution Approach 1:
The patent introduces bridge bonding structures as intermediary elements between die stacks and the substrate. These bridge bonding structures include bond pads and interconnect features that mediate the electrical connections, reducing the complexity of direct die-to-substrate interconnections while maintaining high capacity and performance through the stacked shingled arrangement.
2Productivity
If multiple semiconductor dies are stacked vertically in a shingled arrangement, then capacity increases, but space utilization efficiency worsens due to significant unused space
Solution Approach 1:
The patent implements nested die stacking where multiple semiconductor dies are arranged in shingled configurations within vertical die stacks. Each die is offset and nested within the footprint of the die below it, allowing maximum spatial utilization. This nesting approach enables higher overall capacity within the same package area by eliminating unused space between dies.
Data Source
AI summary
A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.