Bridge Chip Delay Circuit Timing Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor storage devices, variations in RE latency across memory chips can lead to asynchronous data reception when a bridge chip transmits read enable signals simultaneously, complicating parallel read operations and data synchronization.
Innovation Solution
Incorporating first and second delay circuits in the bridge chip to adjust the transmission start timing of read enable signals for each channel, ensuring synchronized data reception from multiple memory chips without the need for FIFO memory, by measuring and compensating for individual RE latency differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read enable signals are transmitted simultaneously to multiple memory chips, then parallel read operations can be initiated, but data reception becomes asynchronous due to RE latency variations
Solution Approach 1:
The bridge chip measures RE latency for each memory chip in advance during a training phase, stores these values, and uses them to pre-calculate compensation delays. This preliminary measurement and storage of latency data enables the bridge chip to proactively adjust signal timing before actual parallel read operations, ensuring synchronized data reception without requiring real-time adjustment mechanisms.
Solution Approach 2:
The bridge chip dynamically adjusts the transmission timing parameter of read enable signals based on stored RE latency measurements. By changing the timing parameter individually for each memory chip's channel, the bridge chip compensates for latency variations and achieves synchronized data reception across all channels, resolving the contradiction between parallel operation efficiency and data synchronization reliability.
2Reliability
If delay circuits are added to adjust transmission timing for each channel, then data synchronization is achieved, but device complexity increases
Solution Approach 1:
Instead of using complex real-time delay adjustment circuits, the bridge chip performs preliminary measurement of RE latency during training and stores these values in memory. This approach replaces complex dynamic adjustment mechanisms with simple lookup-based timing control, achieving synchronization while minimizing additional hardware complexity.
Solution Approach 2:
The patent replaces potential complex hardware delay circuits with a software/firmware-based timing adjustment mechanism. The bridge chip uses stored latency values to control transmission timing through programmable logic or control signals, substituting mechanical or complex electronic delay elements with a more flexible and simpler-to-implement digital control approach.
3Reliability
If RE latency is measured and compensated for each memory chip, then synchronized data reception is achieved, but measurement and control processes become more complex
Solution Approach 1:
The bridge chip performs RE latency measurement during an initial training phase before normal operation begins. This preliminary measurement approach allows the system to characterize each memory chip's latency once, store these values, and reuse them for all subsequent parallel read operations, avoiding the need for continuous complex measurement processes and simplifying ongoing control.
Solution Approach 2:
The bridge chip autonomously measures its own RE latency to each memory chip during training and uses this self-measured data to automatically adjust transmission timing. This self-service approach eliminates the need for external measurement equipment or complex coordinated measurement protocols, simplifying the measurement process while achieving reliable synchronization.
Data Source
AI summary
A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.