Bridge Chip for DRAM-NAND Address Translation
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Solution Overview
Problem
The existing memory systems face challenges in accessing high-density NAND memory due to limitations in address bus capacity, latency differences between DRAM and NAND memory, and the inability to issue simultaneous commands beyond the number of banks, which restricts the control of NAND memory by DRAM controllers.
Innovation Solution
A bridge chip is introduced between the DRAM controller and NAND memory to convert protocols and manage addresses, commands, and data, allowing for the expansion of accessible address space and enabling simultaneous control of multiple commands through the use of a DRAM protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a DRAM controller directly controls NAND memory, then the system structure is simple, but the accessible address space is limited due to address bus capacity
Solution Approach 1:
A bridge chip is introduced as an intermediary component between the DRAM controller and NAND memory. The bridge chip receives addresses from the DRAM controller's address bus and translates them to the corresponding physical addresses in NAND memory, enabling the DRAM controller to access the full address space of NAND memory without requiring a larger address bus.
2Adaptability or versatility
If DRAM and NAND memory operate independently, then each memory type can be optimized, but latency differences cause control difficulties
Solution Approach 1:
The bridge chip serves as a protocol translator and intermediary that handles the latency differences between DRAM and NAND memory. It buffers commands and addresses, translating DRAM controller timing signals into NAND memory-compatible signals, thereby enabling the DRAM controller to effectively control NAND memory despite their different operational characteristics.
3Productivity
If the number of banks is increased to issue simultaneous commands, then command processing capability improves, but the device complexity increases
Solution Approach 1:
The bridge chip segments the command processing function by implementing separate command queues for different memory banks. Each queue can hold commands for a specific bank, allowing the DRAM controller to issue simultaneous commands to multiple banks without increasing the controller's internal bank structure complexity.
4Quantity of substance
If address bus width is increased to access high-density NAND memory, then accessible address space expands, but the cost and complexity of the controller increases
Solution Approach 1:
The bridge chip acts as an address translation intermediary that bridges the gap between the DRAM controller's address bus width and the NAND memory's address requirements. It receives addresses from the controller's address bus and generates the appropriate physical addresses for NAND memory, allowing the controller to maintain its original address bus width while accessing high-density memory spaces.
Data Source
AI summary
A memory system according to the present embodiment includes a memory controller including a first data bus and a first address bus. A memory part includes a second data bus and a second address bus. A bridge part is capable of receiving an address from the memory controller via the first data bus, and outputs the address via the first address bus to the memory part.