Bridge-Chip Interposer Package With Hybrid Bonded Stacked Dies
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Solution Overview
Problem
Current semiconductor packages struggle to meet integration and speed requirements while being miniaturized and lightweight, and they are also costly to manufacture.
Innovation Solution
A semiconductor package design featuring an interposer substrate with a bridge chip, where first and second semiconductor devices are stacked and bonded using metal-metal hybrid bonding, allowing for efficient electrical connections and integration of memory controllers and input/output circuits in a separate bridge chip, reducing manufacturing costs and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If semiconductor packages are miniaturized and lightweight to meet electronic device requirements, then weight and size are reduced, but integration capability and speed performance deteriorate
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking, where multiple semiconductor chips are vertically stacked and connected through the interposer substrate. This vertical dimension enables higher integration without increasing the package footprint, resolving the contradiction between miniaturization and integration capability.
Solution Approach 2:
The interposer substrate serves as an intermediary component between stacked semiconductor chips, providing electrical connections and signal routing. This mediator enables complex inter-chip communication while maintaining a compact structure, thus improving integration capability without compromising the miniaturized form factor.
2Ease of manufacture
If conventional bonding methods are used to connect stacked chips, then manufacturing process is simpler, but manufacturing cost increases and performance is limited
Solution Approach 1:
The patent replaces conventional mechanical bonding methods (such as wire bonding or soldering) with direct metal-metal hybrid bonding. This substitution eliminates intermediate materials and complex bonding processes, reducing manufacturing costs while enabling higher-speed electrical connections and improved performance.
Solution Approach 2:
The interposer substrate employs composite material structure with metal layers for electrical connections. This composite approach combines different material properties to achieve both low-cost manufacturing and high-performance electrical interconnections, resolving the contradiction between ease of manufacture and performance.
3Adaptability or versatility
If memory controllers and I/O circuits are integrated into the main semiconductor chip, then device functionality is complete, but manufacturing cost increases
Solution Approach 1:
The patent segments the semiconductor system into separate functional modules: memory controllers and I/O circuits are placed on the interposer substrate, while memory chips are stacked above. This segmentation allows independent manufacturing and optimization of each component, reducing overall manufacturing cost while maintaining complete device functionality.
Solution Approach 2:
The interposer substrate serves multiple functions: it provides electrical connections between stacked chips, hosts memory controllers and I/O circuits, and enables signal routing. This multi-functionality consolidates several components into one element, reducing the total component count and manufacturing cost while preserving full device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables high integration and speed with reduced costs by utilizing metal-metal hybrid bonding to connect semiconductor chips, enhancing the performance of the process unit and allowing for cost-effective manufacturing.
Implementation Method 1
the interposer bonding pad is metal-metal hybrid bonded to the first chip bonding pad and the second chip bonding pad
Data Source
AI summary
A semiconductor package includes: an interposer substrate in which a bridge chip is mounted; a first semiconductor device on the interposer substrate, the first semiconductor device comprising a first semiconductor chip and a plurality of second semiconductor chips stacked in a first direction; and a second semiconductor device spaced apart from the first semiconductor device in a second direction, where an interposer bonding pad is on a face of the bridge chip, a first chip bonding pad that overlaps at least part of the interposer bonding pad in the first direction is on a face of the first semiconductor chip, and a second chip bonding pad that overlaps part of a remaining interposer bonding pad in the first direction is on a face of the second semiconductor device, and where the interposer bonding pad is metal-metal hybrid bonded to the first chip bonding pad and the second chip bonding pad.