Bridge Chip Packaging With Silicate Dielectric for Alignment Stability
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Solution Overview
Problem
Conventional electronic packaging methods using molding compounds can cause alignment shifts and stress due to thermal expansion coefficient differences between chips and materials, leading to reliability issues and inefficient signal transmission.
Innovation Solution
A manufacturing method involving a temporary carrier, direct bonding of bridge elements to chip pads, and a silicate composite base dielectric layer that fills gaps between chips, reduces interface stress and enhances signal transmission by using materials with low thermal expansion coefficients, allowing for thinner and lighter packages with improved reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If molding compound is used to cover chips and bridge element, then protection is provided, but alignment shift occurs and stress accumulates due to thermal expansion coefficient difference
Solution Approach 1:
The patent changes the material parameter of the dielectric layer from conventional molding compound to a material with thermal expansion coefficient matching the chip substrate (both around 2.55 ppm/°C). This parameter change eliminates the thermal expansion mismatch that causes stress accumulation and alignment shift during curing, while still providing the required protection and encapsulation functions.
Solution Approach 2:
The patent employs a composite material solution by using a dielectric layer composed of specific materials (such as benzocyclobutene or silane-based materials) that combine appropriate mechanical properties with matched thermal expansion characteristics. This composite approach allows simultaneous achievement of protection, stress reduction, and alignment precision.
2Reliability
If molding compound is used to cover chips and bridge element, then protection is provided, but stress accumulates on contact surface due to large difference in thermal expansion coefficient
Solution Approach 1:
The patent fundamentally changes the thermal expansion parameter of the encapsulating material to match the chip substrate (both 2.55 ppm/°C). This parameter matching eliminates the stress accumulation at the chip-material interface that occurs with conventional molding compounds, thereby improving interface reliability without compromising protection.
Solution Approach 2:
The patent applies different material qualities to different regions: the dielectric layer directly contacting the chip substrate uses material with matched thermal expansion properties to minimize stress, while the encapsulating material provides protection. This local quality differentiation optimizes both interface reliability and overall protection.
3Speed
If bridge element overlaps with adjacent chips, then signal transmission path is shortened, but complexity of packaging structure increases
Solution Approach 1:
The patent merges the bridge element structure with the chip substrate by allowing the bridge element to overlap directly with adjacent chips and bond to their active surfaces. This merging eliminates the need for separate redistribution layers and complex routing structures, shortening the signal transmission path while actually simplifying the overall packaging structure through direct bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves high reliability and performance by minimizing interface stress and alignment shifts, improving signal transmission efficiency and power consumption, and enabling high-density bridging for advanced computing applications.
Implementation Method 1
A material of the base dielectric layer is a silicate composite material or a material available for chemical-mechanical polishing. The material of the base dielectric layer can reduce the interface stress between the material and each chip
Implementation Method 2
A material of the base dielectric layer is a silicate composite material or a material available for chemical-mechanical polishing. The bridge element and the base dielectric layer are thinned and planarized
Implementation Method 3
Multiple bridging pads of the bridge element are respectively directly bonded to multiple first chip pads of the active surfaces of the adjacent chips. The direct copper bond of the bridge element to the chips also helps to drastically improve transmission performance
Data Source
AI summary
A manufacturing method of an electronic package includes the following steps. Multiple chips are temporarily fixed to a temporary carrier. At least one bridge element is installed on the adjacent chips. A base dielectric layer covering a temporary bonding layer, the chips, and the bridge element is formed. A material of the base dielectric layer includes a silicate composite material. Multiple base conductive vias and a redistribution structure are respectively formed on the chips and the base dielectric layer. Multiple conductive bumps are formed on the redistribution structure. In addition, an electronic package is also provided, which may be produced by the manufacturing method.