Bridge Chip PLL Clock Switching for Data Strobe Jitter Control
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Solution Overview
Problem
Semiconductor storage devices face issues with data strobe signal jitter during data transfer between the host and memory chips, leading to incorrect data reception due to the lack of effective clock signal quality, especially when no transfer data is being transferred.
Innovation Solution
Incorporating a phase-locked loop (PLL) circuit in the bridge chip to generate a new clock signal by using the data strobe signal as a reference, and an oscillator to provide a high-quality clock during non-transfer periods, thereby reducing jitter and ensuring accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data strobe signal is used directly as the clock signal for data transfer, then the data transfer speed can be maintained, but jitter accumulates leading to incorrect data reception
Solution Approach 1:
A PLL circuit is introduced as an intermediary between the data strobe signal and the memory chip to generate a clean clock signal. The PLL circuit receives the data strobe signal as reference, filters out jitter through its phase-locked loop mechanism, and outputs a stable clock signal for data transfer, thus ensuring reliable data reception without directly using the jittered strobe signal
Solution Approach 2:
The system creates a copy of the data strobe signal through the PLL circuit to generate a new clock signal that has the same frequency and phase characteristics but without the accumulated jitter. This copied clock signal is then used for data transfer, separating the timing function from the original strobe signal that carries data
2Use of energy by moving object
If no clock signal is provided during non-transfer periods, then power consumption is reduced, but jitter cancellation capability is lost when transfer resumes
Solution Approach 1:
The system dynamically controls the PLL circuit based on transfer requirements. During active data transfer periods, the PLL circuit is enabled to cancel jitter and provide stable clock signals. During non-transfer periods, the PLL circuit is disabled to reduce power consumption. This dynamic switching maintains reliability when needed while optimizing power efficiency
3Reliability
If the PLL circuit continuously operates to maintain clock signal quality, then jitter is consistently canceled, but power consumption increases during non-transfer periods
Solution Approach 1:
The PLL circuit operates periodically rather than continuously - it is activated only during data transfer periods when clock signal quality is needed for jitter cancellation, and deactivated during non-transfer periods. This periodic operation maintains clock signal quality during critical transfer windows while significantly reducing average power consumption during idle times
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PLL circuit effectively cancels jitter in the data strobe signal, allowing memory chips to receive data with reduced errors and maintaining high-quality clock signals even during periods without data transfer, thus enhancing data transfer reliability and speed.
Implementation Method 1
a phase-locked loop circuit to generate a clock signal
Data Source
AI summary
A semiconductor integrated circuit includes a register, a first interface circuit, an oscillation circuit that generates a first clock, a pll circuit, a control circuit, and a second interface circuit. The register stores numerical information representing a data size. The first interface circuit receives, from a first device, a first timing signal for data transfer. Responding to receipt of the first timing signal, the control circuit inputs the first timing signal to the pll circuit and counts the number of toggles of the first timing signal. When a counted number of toggles of the first timing signal matches a value corresponding to the numerical information, the control circuit inputs the first clock to the pll circuit. The second interface circuit transmits, to a second device, the first timing signal or a second timing signal, which corresponds to a second clock generated based on the first clock by the pll circuit.