Bridge Chip Semiconductor Package With Self-Aligned Conductive Posts
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Solution Overview
Problem
Semiconductor packages face challenges in reducing process costs while maintaining high reliability and performance, particularly in achieving size reduction and stable power supply as they become more compact and lightweight.
Innovation Solution
A semiconductor package design incorporating a redistribution structure with a single-layer passivation layer, under bump metallurgy (UBM) layer, conductive layer, bridge chip, and conductive posts that enable self-alignment and efficient electrical connections between semiconductor chips, along with a molding layer for sealing and stabilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer passivation layer is used instead of multi-layer structures, then manufacturing complexity and process costs are reduced, but protection and reliability may be compromised
Solution Approach 1:
The patent combines multiple functions (protection, adhesion, stress relief) into a single passivation layer structure. This single layer integrates the protective barrier function against moisture and contaminants while also providing stress management capabilities, eliminating the need for separate multi-layer structures and reducing manufacturing complexity.
Solution Approach 2:
The passivation layer is designed to perform multiple functions simultaneously: it provides environmental protection, mechanical stress relief, and electrical insulation in a single structure. This multi-functional design reduces the number of required layers while maintaining or improving overall reliability.
2Manufacturing precision
If conductive posts with self-alignment features are used, then manufacturing precision and alignment accuracy are improved, but device complexity increases
Solution Approach 1:
The conductive posts incorporate self-alignment features that enable automatic positioning during the assembly process. The posts are designed with geometric characteristics that allow them to self-align with corresponding structures without requiring complex external alignment mechanisms or additional processing steps.
Solution Approach 2:
The conductive posts are designed with symmetric geometric features that create equipotential alignment conditions, where the posts naturally align with corresponding structures due to their uniform shape and positioning features, simplifying the overall alignment process.
3Volume of moving object
If semiconductor packages are made more compact and lightweight, then size reduction is achieved, but power consumption increases
Solution Approach 1:
The patent transitions from horizontal expansion to vertical stacking architecture, arranging semiconductor chips and conductive posts in three-dimensional space. This vertical integration allows compact packaging while maintaining efficient electrical connections and power distribution pathways, reducing the power required for signal transmission.
Solution Approach 2:
The design nests multiple functional elements within a compact volume, placing conductive posts, semiconductor chips, and connection structures in a vertically integrated configuration. This nested arrangement maximizes space utilization while minimizing the overall package size and associated power consumption.
4Reliability
If more conductive posts are added for better electrical connections, then electrical conductivity improves, but manufacturing complexity and cost increase
Solution Approach 1:
The conductive posts are designed with self-alignment capabilities that allow them to automatically position themselves during assembly. This self-positioning feature eliminates the need for complex alignment mechanisms or additional alignment-related components, maintaining electrical connection reliability while controlling overall complexity.
Solution Approach 2:
The patent optimizes the geometric parameters of conductive posts, such as diameter, height, and spacing, to achieve the required electrical conductivity with the minimum necessary number of posts. By carefully controlling these parameters, the design achieves reliable electrical connections without unnecessarily increasing component count.
Data Source
AI summary
A semiconductor package includes a redistribution structure including: a passivation layer; an under bump metallurgy (UBM) layer on a portion of a lower surface of the passivation layer; and a conductive layer in contact with the UBM layer and exposed from an upper surface of the passivation layer opposite to the lower surface of the passivation layer. The semiconductor package further includes: a bridge chip on the redistribution structure and including a bridge chip pad; a first molding layer sealing the bridge chip on the redistribution structure; conductive posts spaced apart from each other in a horizontal direction within the first molding layer, the bridge chip being between the conductive posts and each of the conductive posts; and a semiconductor chips on the first molding layer and the bridge chip, each of the semiconductor chips including a chip pad and a solder bump.