Bridge-Chip Semiconductor Package With Staggered Solder Pitch
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Solution Overview
Problem
There is a need for semiconductor packages that offer increased operating stability and electrical properties while reducing size and weight, necessitating advanced packaging technologies that integrate multiple devices into a single compact package with optimized solder heights and intervals for efficient electrical connections.
Innovation Solution
A semiconductor package design featuring a package substrate with a core portion, an upper buildup portion, and a bridge chip, where the bridge chip has pads with higher integration density than the substrate pads, allowing for high-density electrical connections through smaller connection terminals, and a molding layer surrounds the chips for enhanced stability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If multiple devices are integrated into a single package to reduce size and weight, then portability is improved, but the risk of electrical shorts between devices increases
Solution Approach 1:
The patent implements a multi-layer stacked package structure where semiconductor devices are vertically nested across multiple layers (first layer, second layer, third layer). Each layer contains devices that are electrically isolated from others, allowing high-density integration while maintaining reliability through vertical stacking rather than horizontal placement.
Solution Approach 2:
The patent introduces a mold compound as an intermediary material that fills the spaces between stacked semiconductor devices. This mold compound provides electrical insulation between adjacent devices on different layers, preventing electrical shorts while mechanically supporting the integrated structure.
2Area of stationary object
If devices are placed closer together to increase integration density, then package size is reduced, but the likelihood of electrical shorts increases
Solution Approach 1:
The patent transitions from two-dimensional horizontal device placement to three-dimensional vertical stacking. Devices are arranged across multiple vertical layers (first layer, second layer, third layer), enabling high integration density within a compact footprint while maintaining adequate electrical isolation through vertical separation.
Solution Approach 2:
The mold compound serves as an intermediary insulating material that fills the gaps between vertically stacked devices. This allows devices to be positioned in close proximity while the mold compound prevents electrical shorts by providing dielectric isolation between adjacent devices on different layers.
3Reliability
If solder heights are increased to improve electrical connections, then connection reliability is improved, but the package height increases
Solution Approach 1:
The patent distributes electrical connections across multiple vertical layers rather than relying on tall solder joints. Solder bumps connect devices to substrates within the same layer, while vertical interlayer connections are achieved through controlled vias and conductive pathways in the mold compound, eliminating the need for excessive solder height.
Solution Approach 2:
The patent segments the electrical connection path into multiple shorter stages: solder bumps connect devices to substrate pads within each layer, and separate conductive pathways in the mold compound connect between layers. This segmentation replaces the need for single tall solder joints with multiple shorter connection segments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical properties and operating stability by enabling high-integration density connections without electrical shorts, reducing manufacturing costs, and achieving compact, high-performance semiconductor packages.
Implementation Method 1
First solders couple the first device to the first pads and second solders couple the first device to the second pads
Implementation Method 2
A molding layer is on the substrate. The molding layer surrounds the first semiconductor chip and the chip stack
Implementation Method 3
Top surfaces of the first and second pads are positioned at a level higher than a level of top surfaces of the third and fourth pads
Data Source
AI summary
A semiconductor package includes a package substrate. A first device is on the package substrate. A second device is on the package substrate and is horizontally spaced apart from the first device. The package substrate includes a core portion. A bridge chip is on a top surface of the core portion. The bridge chip has first pads. An upper buildup portion covers the top surface of the core portion and surrounds the bridge chip. The upper buildup portion has second pads. First solders couple the first device to the first pads and second solders couple the first device to the second pads. A first height of the first solders is less than a second height of the second solders. A first interval between adjacent first solders of the first solders is less than a second interval between adjacent second solders of the second solders.