Semiconductor Package Bridge Chip Structure for Warpage Reduction
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Solution Overview
Problem
Warpage occurs in semiconductor packages due to mismatched thermal expansion coefficients between the interposer and semiconductor devices, particularly in 2.5D packages like 2.3D, where logic and memory semiconductor devices are connected via silicon bridge chips.
Innovation Solution
Incorporating a bridge chip with a convex bump structure made of silicon material in the interposer, which has a higher thermal expansion coefficient than the sealing member, to balance the overall thermal expansion and reduce warpage by increasing the silicon die portion's space ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an interposer with redistribution wiring layer is used to provide high-density interconnections, then connection density is improved, but warpage occurs due to thermal expansion coefficient mismatch
Solution Approach 1:
The bridge chip is designed with non-uniform thickness, featuring a thicker middle region and thinner peripheral region. This local quality variation allows the middle region to have different thermal expansion characteristics compared to the periphery, enabling localized compensation for thermal stress and reducing overall warpage while maintaining high-density interconnections.
Solution Approach 2:
The invention uses a composite structure combining the interposer substrate with a bridge chip made of silicon material having different thermal expansion properties. This composite material approach creates a balanced thermal expansion system where the silicon bridge chip compensates for the thermal mismatch between the interposer and mounted semiconductor devices, reducing warpage.
2Reliability
If a bridge chip is added to connect logic and memory semiconductor devices, then electrical connection is improved, but thermal expansion mismatch is worsened
Solution Approach 1:
The bridge chip's physical parameters, particularly its thickness distribution (thicker middle, thinner periphery) and material composition (silicon), are specifically designed to change the thermal expansion characteristics of the overall package. This parameter optimization allows the bridge chip to serve dual functions: providing reliable electrical connections through its wiring layer while simultaneously adjusting the thermal expansion profile to reduce mismatch effects.
3Stability of the object's composition
If the bridge chip has a convex bump structure with higher thermal expansion coefficient, then thermal expansion balance is improved, but manufacturing complexity increases
Solution Approach 1:
The bridge chip features a convex bump structure with a curved surface profile, where the middle region protrudes upward to form a dome-like shape. This curvature design is achieved through controlled thickness variation during manufacturing, allowing the convex structure to provide thermal expansion compensation while using standard semiconductor fabrication processes.
Solution Approach 2:
The bridge chip structure is segmented into distinct functional regions: a thicker middle region containing the bump structure for thermal compensation, and a thinner peripheral region for mounting connections. This segmentation allows each region to be optimized independently for its specific function while being manufactured as an integrated component.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The convex bump structure reduces thermal expansion mismatch, minimizing warpage and enhancing the structural integrity of semiconductor packages by matching thermal expansion coefficients between upper and lower portions.
Implementation Method 1
Warpage occurs due to a difference in thermal expansion coefficient between individual components (e.g., a redistribution wiring layer) constituting the interposer and a semiconductor device mounted on the interposer
Data Source
AI summary
A semiconductor package includes a lower redistribution wiring layer, a bridge chip provided on the lower redistribution wiring layer and having a bump structure, a sealing member covering the bridge chip on the lower redistribution wiring layer, a plurality of vertical conductive structures around the bridge chip and penetrating the sealing member, an upper redistribution wiring layer disposed on the sealing member, a first semiconductor device mounted on the upper redistribution wiring layer, and a second semiconductor device mounted on the upper redistribution wiring layer and spaced apart from the first semiconductor device, the second semiconductor device being electrically connected to the first semiconductor device by the bridge chip.


