Bridge Circuit Control Signal Integration for Peripheral Reusability
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Solution Overview
Problem
Semiconductor integrated circuit devices face challenges in managing diverse and complex control signals for peripheral circuits, which decreases reusability as the number of peripheral circuits increases, and requires modifications when reused in different systems.
Innovation Solution
A bridge circuit is introduced, comprising a first interface block, a second interface block, a clock detection block, and a state machine that receives and decodes a frequency-divided clock signal to generate synchronized control signals for peripheral circuits, thereby integrating control signals and increasing reusability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control signals for each peripheral circuit are generated independently, then each peripheral circuit can be controlled precisely, but the control signal generation becomes increasingly complex and diverse as the number of peripheral circuits increases
Solution Approach 1:
The patent merges the control signal generation functions for multiple peripheral circuits into a single integrated state machine. The state machine receives a single clock signal and generates all necessary control signals (HCLK, HRESET, HREADY, HTRANS, HWRITE, HSEL) in a unified manner, eliminating the need for separate control signal generation circuits for each peripheral device.
Solution Approach 2:
The state machine is designed as a universal control unit that can generate control signals for multiple different types of peripheral circuits simultaneously. By using a single clock signal and a unified state machine, the system achieves multi-functionality where one control unit serves multiple peripheral devices with different requirements.
2Adaptability or versatility
If peripheral circuits are customized for specific systems, then they can meet specific system requirements, but their reusability in different systems decreases
Solution Approach 1:
The bridge circuit with its unified state machine and clock signal generation serves as a universal interface that can work with multiple different peripheral circuits. The peripheral circuits themselves can be designed with standard interfaces that work with this universal bridge, making them reusable across different system configurations without customization.
Solution Approach 2:
The bridge circuit acts as an intermediary between the CPU and various peripheral circuits. It translates and synchronizes control signals, allowing peripheral circuits to maintain standard designs while adapting to different system requirements through the bridge's signal translation capabilities rather than modifying the peripheral circuits themselves.
3Adaptability or versatility
If multiple peripheral circuits are connected to the same bus, then system integration is improved, but control signal synchronization becomes more difficult
Solution Approach 1:
The patent combines all control signal generation for multiple peripheral circuits into a single state machine driven by one clock signal. This unified approach automatically handles synchronization across all peripheral circuits without requiring separate synchronization mechanisms for each device.
Solution Approach 2:
The state machine uses feedback from the clock signal and system state to automatically adjust and synchronize control signals for multiple peripheral circuits. The unified control unit monitors system conditions and generates appropriately synchronized control signals for all connected peripherals based on the single clock reference.
Data Source
AI summary
A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response to a first clock signal, a first bus connected to the CPU, a bridge circuit connected to the first bus, a second bus connected to the bridge circuit, a plurality of peripheral circuits connected to the second bus, and a clock monitor connected to the first bus or the second bus and configured to output a register value corresponding to a second clock signal to the bridge circuit. The bridge circuit receives the first control signals, generates second control signals based on the register value, and outputs the second control signals to one of the peripheral circuits via the second bus.