Interface Bridge Circuit for Deadlock Avoidance in Mixed Coherency Systems
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Solution Overview
Problem
Processor-based systems employing both retry and in-order-response non-retry bus coherency protocols face deadlocks due to dependency issues between snoop commands and write operations, particularly when using different coherency protocols like proprietary and ACE protocols, leading to potential system bottlenecks and inefficiencies.
Innovation Solution
An interface bridge circuit is introduced to detect and mitigate potential deadlock conditions by sending a retry response to the first core device when a snoop command from a retry bus coherency protocol core device encounters a pending write operation or timer expiration while communicating with an in-order-response non-retry bus coherency protocol core device, ensuring seamless operation without modifying existing protocols or devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a processor-based system employs both retry bus coherency protocol and in-order-response non-retry bus coherency protocol, then the system can support diverse core devices with different performance requirements, but deadlock conditions occur due to dependency issues between snoop commands and write operations
Solution Approach 1:
The interface bridge circuit acts as an intermediary between core devices using retry protocol and core devices using in-order-response non-retry protocol. It monitors snoop commands from retry protocol devices, detects potential deadlocks by checking for address collisions with pending write operations, and sends retry responses to prevent deadlocks. This mediator approach enables protocol diversity while maintaining system reliability.
2Device complexity
If a core device implements in-order-response non-retry bus coherency protocol, then the protocol complexity is reduced and processing is simplified, but dependencies exist between snoop commands and write operations that can cause deadlocks
Solution Approach 1:
The interface bridge circuit serves as an intermediary that compensates for the simplicity of in-order-response non-retry protocol by handling deadlock detection and prevention. It monitors snoop commands, detects address collisions with pending write operations, and sends retry responses to break potential deadlocks, allowing the simple protocol to operate reliably in mixed-protocol systems.
3Productivity
If a core device implements retry bus coherency protocol, then the device can handle complex operations and maintain timing flexibility, but potential deadlock conditions arise when waiting for snoop responses
Solution Approach 1:
The interface bridge circuit implements feedback by monitoring snoop commands from retry protocol devices and detecting potential deadlocks through address collision detection with pending write operations. When a deadlock condition is detected, the bridge sends a retry response back to the requesting core device, providing feedback that breaks the deadlock and allows the device to continue processing.
4Reliability
If the system allows snoop commands to wait for responses without timeout, then complete data consistency is ensured, but system efficiency decreases due to potential indefinite waiting
Solution Approach 1:
The interface bridge circuit performs preliminary action by proactively detecting potential deadlock conditions before they manifest as actual deadlocks. It monitors snoop commands and checks for address collisions with pending write operations, sending retry responses in advance to prevent indefinite waiting. This preliminary detection and intervention maintains both data consistency and system efficiency.
Data Source
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AI summary
Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.