Bridge Circuitry for Memory Transaction Translation
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Solution Overview
Problem
Data processing systems face challenges in efficiently translating memory transactions between different types, such as PCI Express and AMBA AXI formats, due to mismatched attribute data support, leading to inflexibility and resource bottlenecks in translation lookaside buffers.
Innovation Solution
The implementation of bridge circuitry with translation circuitry that maps attribute data from memory transactions of one type into unused bits of the address space of another type, allowing for flexible translation and reducing the burden on system memory management units by using local translation caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a system memory management unit with translation lookaside buffer is used to translate memory transactions, then address translation can be performed, but the translation lookaside buffer becomes a resource bottleneck when the number of transaction sources and destinations increases
Solution Approach 1:
The patent divides the translation function into two segments: local translation caches within individual bus masters and a system memory management unit. This segmentation allows each bus master to handle its own translation requests independently, eliminating the bottleneck of a single centralized translation lookaside buffer while maintaining address translation capability.
2Adaptability or versatility
If local translation caches are provided within bus masters, then address translation can be performed without requiring system memory management unit resources, but attribute data from the first transaction type has no counterpart in the second transaction type format
Solution Approach 1:
The patent embeds attribute data into the address field of the second transaction type, utilizing unused bits within the address space. This dimensional transformation allows attribute information to be carried within the address structure itself, resolving the format mismatch problem while enabling local translation caches to function independently.
3Adaptability or versatility
If attribute data is mapped to unused bits in the address space of the second transaction type, then flexible translation can be achieved without system memory management unit involvement, but the address space must have sufficient unused bits available
Solution Approach 1:
The patent copies attribute data from the first transaction type into the unused bits of the address field in the second transaction type. This copying mechanism preserves all necessary attribute information while utilizing otherwise wasted address space, achieving flexible translation without losing address information.
Data Source
AI summary
A data processing apparatus 2 includes bridge circuitry 14, 16, 18 which serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitry 18 which maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.