Bridge Connector for Multi-Chip Module Interconnects
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Solution Overview
Problem
Current interconnection technologies between semiconductor chips face limitations in density, bandwidth, and complexity, particularly as chip sizes decrease and bandwidth requirements increase, necessitating designs that maximize connections per surface area and minimize connection distance and overlap.
Innovation Solution
The development of a bridge connector with semiconductor layers and contacts positioned to overlap interior corners of chips, allowing direct connections between non-adjacent chips while minimizing surface area coverage and maintaining access for cooling and additional connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If optical connections are used to handle high bandwidths, then bandwidth capability is improved, but efficiency deteriorates due to conversions between electrical and optical signals and increased manufacturing complexity
Solution Approach 1:
The patent introduces an interposer layer as an intermediary component between chips that provides electrical signaling capabilities while enabling higher bandwidth through improved interconnect geometry. The interposer acts as a mediator that resolves the contradiction by providing electrical connections with better performance characteristics rather than converting to optical signals.
Solution Approach 2:
The patent employs 2.5D integration technology that adds a vertical dimension to interconnections through the interposer layer, allowing signals to travel through multiple layers and achieving higher bandwidth without requiring optical conversion. This dimensional approach enables parallel interconnect paths that increase data throughput.
2Quantity of substance
If the number of chip contacts and contact pitch are increased to maximize connections per surface area, then connection density is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The interposer layer serves as an intermediary that absorbs the manufacturing precision requirements through its own larger feature sizes and relaxed pitch dimensions. By placing contacts on the interposer at larger pitch than on the chips themselves, the system achieves high connection density while reducing the precision demands on chip fabrication processes.
3Quantity of substance
If interposers are used to enable high densities of connections and accommodate higher bandwidth requirements, then connection density and bandwidth are improved, but device complexity worsens as the number of connections within the interposer increase
Solution Approach 1:
The patent segments the interconnection system into distinct functional layers: chip interfaces, interposer routing layers, and package interfaces. This segmentation allows each layer to be optimized independently, reducing overall system complexity while maintaining high connection density. The interposer is divided into multiple conductive layers that can be routed independently.
Solution Approach 2:
The patent utilizes 2.5D integration that employs multiple horizontal and vertical routing layers within the interposer, transforming a potentially complex planar connection problem into a multi-layered solution. This approach organizes numerous connections in three dimensions, making the system more manageable and less complex than attempting to route all connections in a single plane.
4Power
If silicon-bridge technology is used to enable high-bandwidth communication between chips, then bandwidth is improved, but package complexity and substrate processing worsen
Solution Approach 1:
The interposer acts as an intermediary substrate that simplifies package complexity compared to silicon-bridge technology. Instead of requiring complex silicon bridge structures and advanced substrate processing, the interposer uses standard semiconductor fabrication processes to create a manageable intermediate platform for high-bandwidth connections.
Data Source
AI summary
The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.