Bridge Control Chip Command Sorting for Flash Memory Efficiency
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Solution Overview
Problem
The processing complexity of flash memory devices is increased due to multiple read/write commands from a USB host that do not follow a specific logical address rule, degrading performance in conventional USB attached SCSI protocols.
Innovation Solution
A bridge control chip with a processor that sorts received read/write commands based on their logical address distance from the currently executed command, ensuring sequential transmission to a UFS device, thereby improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple read/write commands are transmitted from USB host to flash memory device without sorting, then the host can issue commands freely, but the processing complexity of the flash memory device increases and performance degrades
Solution Approach 1:
The bridge control chip acts as an intermediary between the USB host and the flash memory device. It receives unordered read/write commands from the host, sorts them according to logical address proximity, and transmits the sorted commands to the flash memory device. This mediator approach allows the host to issue commands freely while the bridge handles the sorting complexity, protecting the flash memory device from processing complexity.
Solution Approach 2:
The system is segmented into three functional parts: the USB host that issues commands, the bridge control chip that sorts commands, and the flash memory device that executes commands. By dividing the command processing function across these segments, the patent allows each component to specialize - the host focuses on command generation, the bridge on sorting, and the flash device on execution - thereby reducing overall system complexity while maintaining versatility.
2Productivity
If multiple read/write commands are transmitted from USB host to flash memory device without sorting, then command transmission is simple, but the processing speed and efficiency of the flash memory device decrease
Solution Approach 1:
The bridge control chip performs preliminary sorting of read/write commands based on logical address proximity before transmitting them to the flash memory device. By preparing the commands in advance in an optimized sequence, the flash memory device can execute them more efficiently without needing to handle the sorting complexity during execution, thereby improving processing speed while managing complexity at the bridge level.
3Productivity
If the flash memory device processes unordered read/write commands directly, then no additional processing is needed, but the overall system efficiency decreases
Solution Approach 1:
The bridge control chip serves as an intermediary that enhances overall system efficiency by sorting commands before they reach the flash memory device. Although this adds control logic to the bridge, it significantly improves flash memory device performance and overall system throughput, making the trade-off favorable.
Solution Approach 2:
The bridge control chip changes the parameter of command sequence by sorting commands according to logical address proximity. This parameter transformation converts unordered commands into a sequentially optimized sequence, improving flash memory device efficiency while concentrating the complexity in the bridge control logic.
Data Source
AI summary
A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.