Bridge Device for Page-Access Processor Interface Translation
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Solution Overview
Problem
NAND flash memory devices are limited in their ability to access data randomly due to their physical arrangement, restricting their use to specific storage devices and applications, and existing interfaces like SDIO only enable additional functions by ensuring all devices comply with a common standard, limiting the versatility of processors designed for NAND storage.
Innovation Solution
A bridge device with multiple interfaces and a switchable communication path allows a page-access based processor to communicate with non-page access memory devices and functions using standard and custom commands, enabling access beyond its intended interface capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor is designed with a NAND-specific interface, then it can efficiently access NAND storage devices, but it is limited to only accessing NAND storage devices or specialized devices
Solution Approach 1:
The processor is designed with a universal interface architecture that can operate in multiple modes: NAND-specific mode for efficient NAND storage access, and extended mode that supports SDIO and other non-NAND devices. The interface includes configurable control logic and data paths that adapt to different device types, allowing the same processor to serve both specialized storage functions and general-purpose I/O functions without requiring separate dedicated interfaces
2Adaptability or versatility
If the interface is extended to SDIO standard, then additional I/O functions are enabled, but all devices must comply with a same standard which limits versatility
Solution Approach 1:
A bridge device or interface adapter is introduced between the processor and external devices. This intermediary component handles the complexity of standard compliance and protocol translation, allowing the processor to access both SDIO-standard devices and non-standard devices through a unified interface. The bridge manages command sequencing, data formatting, and control signal generation, freeing the processor from needing to directly implement multiple device protocols
3Speed
If NAND devices use onboard buffers for data storage, then rapid random access is improved, but the physical arrangement of storage cells remains not conducive to rapid random access
Solution Approach 1:
The memory system is segmented into multiple independent page buffers, each capable of holding a page of data. The interface architecture divides the address space and data paths into separate channels that can be independently configured. This segmentation allows the system to optimize for page-based access patterns while also supporting random access to individual bytes or words by selecting appropriate buffers and using address translation logic to map logical addresses to physical buffer locations
Data Source
AI summary
An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and a configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.