Bridge Die Anchor Layer for Multi-Die Alignment Stability
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Solution Overview
Problem
The challenge of die shift and layer-to-layer interconnect misalignment in multi-die IC packages due to increased transistor density and die segregation, leading to manufacturing complexity and cost issues.
Innovation Solution
Incorporating a liner or anchor layer made of materials like silicon, nitrogen, oxygen, and carbon around the base die to prevent die shift during assembly, using conductive pillars and interconnects for electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a liner or anchor layer is added around the base die to prevent die shift, then manufacturing precision and alignment are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
A liner layer made of silicon nitride or silicon oxynitride is introduced as an intermediary material between the base die and the surrounding structure. This liner layer serves as a mediator that prevents die shift during assembly while managing thermal expansion differences between the die and package substrate, thereby improving alignment precision without requiring complex mechanical constraints
Solution Approach 2:
The anchor layer is formed around the base die before the die is fully assembled into the final package structure. This preliminary formation of the anchor layer constrains the die in advance, preventing shift during subsequent assembly steps and ensuring precise alignment with interconnect bridges before final bonding occurs
2Productivity
If transistor density increases and dies become smaller, then integration capability is improved, but manufacturing precision and alignment difficulty worsen
Solution Approach 1:
The patent introduces a vertical dimension solution by forming the liner and anchor layers in the depth dimension around the base die. Instead of attempting to control horizontal alignment through more complex planar features, the liner layer provides vertical confinement and lateral positioning through its thickness and lateral extent, enabling precise alignment even as die sizes shrink to 7nm and below
Solution Approach 2:
The liner layer material properties are specifically selected (silicon nitride or silicon oxynitride) to match thermal expansion characteristics with the base die. This parameter matching prevents thermal mismatch-induced misalignment during temperature cycling, maintaining alignment precision as transistor density increases and feature sizes decrease
3Device complexity
If conventional multi-die assembly is used without anchor layer, then device complexity is reduced, but die shift and interconnect misalignment occur reducing reliability
Solution Approach 1:
The liner and anchor layers are formed beforehand to create a protective constraint structure around the base die. This pre-formed anchor structure cushions against potential die shift during assembly, preventing misalignment with interconnect bridges before it can occur, thereby ensuring reliable electrical connections without requiring post-assembly correction
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate having a cavity; a first die at least partially nested in the cavity in the first layer of the substrate, the first die having a surface with conductive contacts; a liner layer on the first layer, in a portion of the cavity, and on and around the first die, wherein a material of the liner layer includes: silicon or aluminum, and one or more of nitrogen, oxygen, and carbon; a second layer on the liner layer, wherein the second layer extends into the cavity and is on and around the first die; and a second die on the second layer, wherein the second die is electrically coupled to the conductive contacts on the first die by conductive vias through the second layer and the liner layer.