Semiconductor Package Bridge Die for Fine-Pitch Chip Self-Alignment
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Solution Overview
Problem
The challenge in semiconductor packaging is to minimize the size of the package while ensuring reliable connection reliability between highly integrated semiconductor chips with a large number of input/output terminals, which is difficult due to the miniaturization of semiconductor chips and the increased number of signal terminals.
Innovation Solution
A method of manufacturing a semiconductor package that self-aligns semiconductor chips on pads with fine gaps using the surface tension of solder bumps, forming a bridge die that overlaps the chips vertically, and using a redistribution layer to connect external terminals, thereby reducing the distance between chips and enhancing connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips are miniaturized with increased number of connection terminals, then the integration capacity and functionality are improved, but the connection reliability and manufacturing difficulty deteriorate
Solution Approach 1:
A bridge die is introduced as an intermediary component between the semiconductor chips and the external environment. The bridge die includes a bridge substrate with connection bumps that connect to pads on the semiconductor chips, and redistribution layers that route signals to external terminals. This intermediary structure distributes the connection stress and simplifies the bonding process, thereby improving connection reliability while maintaining high integration capacity.
Solution Approach 2:
The package structure is segmented into distinct functional layers: semiconductor chips mounted on a carrier substrate, a bridge die positioned above the chips with its own substrate and connection structure, and a molding layer encapsulating the assembly. This segmentation allows each component to be optimized independently and facilitates the use of self-alignment techniques during manufacturing, improving both reliability and manufacturability.
2Volume of moving object
If the distance between semiconductor chips is minimized to reduce package size, then the package compactness is improved, but the alignment precision and connection reliability deteriorate
Solution Approach 1:
The solder bumps on the bridge die and the corresponding pads on the semiconductor chips are designed to self-align during the bonding process. The surface tension and wetting characteristics of the solder material cause it to naturally flow and fill the gap between misaligned features, automatically correcting small positioning errors. This self-alignment mechanism enables minimal chip spacing while maintaining high alignment precision without requiring complex external alignment equipment.
3Quantity of substance
If fine gaps between pads are used to increase terminal density, then the I/O capacity is improved, but the solder bump placement precision and connection reliability worsen
Solution Approach 1:
The bonding process parameters are optimized to accommodate fine gaps between pads. The solder bumps are designed with specific size, composition, and melting point characteristics that enable them to flow and wet the pad surfaces effectively even when the gaps are very small. By controlling parameters such as reflow temperature profile, solder bump diameter, and pad metallization layer thickness, the process achieves reliable bonding with high terminal density while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the size of the semiconductor package by minimizing the distance between chips and ensures reliable connection reliability through self-alignment and the use of a bridge die, addressing the challenge of accommodating numerous signal terminals within the package.
Implementation Method 1
arranging, on the plurality of sacrificial pads, a plurality of semiconductor chips disposed to be parallel to each other, each of the plurality of semiconductor chips including a plurality of first metal pillars and a plurality of sacrificial solder bumps disposed below the plurality of first metal pillars; bonding the plurality of sacrificial solder bumps to the plurality of sacrificial pads corresponding thereto between the plurality of semiconductor chips and the first carrier substrate, wherein the plurality of first metal pillars and the plurality of sacrificial pads are self-aligned with each other due to surface tension of the plurality of sacrificial solder bumps
Data Source
AI summary
A method of manufacturing a semiconductor package according to embodiments of the present disclosure has an effect of reducing the size of the semiconductor package by minimizing a distance between semiconductor chips by self-aligning the semiconductor chips on pads having fine gaps due to the surface tension of solder bumps.