Bridge Die Overlap Structure for Compact Stacked Chip Interconnects

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor packages face challenges in ensuring reliable interconnection between multiple semiconductor chips, particularly in stacked configurations, which can lead to increased size and reduced memory capacity due to the need for separate interposers and inefficient use of space.

Innovation Solution

A semiconductor package design that includes a bridge die with overlapping bridge portions extending beyond the edge of a semiconductor chip, connected via vertical conductive structures, to reduce the area occupied by the chip and enhance interconnection, allowing for increased memory capacity and improved structural reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate interposer is used to connect multiple semiconductor chips, then interconnection between chips is guaranteed, but the package size increases and memory capacity decreases

Engineering Contradiction:
Improveinterconnection reliabilityVSAvoidpackage area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the interposer function with the bridge die structure by integrating redistribution layers and interconnection structures directly into the bridge die substrate. This consolidation eliminates the need for a separate interposer component while maintaining reliable electrical connections between stacked semiconductor chips, thereby reducing overall package area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bridge die serves multiple functions simultaneously: it acts as a mechanical support substrate, provides electrical interconnection through redistribution layers, and enables vertical stacking of memory chips. This multi-functionality replaces the traditional separate interposer while achieving both reliable interconnection and compact package size.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the bridge die extends beyond the semiconductor chip edge, then interconnection reliability is improved, but the chip area occupied increases

Engineering Contradiction:
Improvestructural reliabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent resolves the area conflict by utilizing the vertical dimension for bridge die extension. The bridge die protrudes beyond the semiconductor chip edges in the horizontal plane, but this extension is compensated by vertical stacking of multiple memory chips on the same footprint, effectively converting horizontal area consumption into vertical space utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The bridge die structure is designed to overlap partially with the semiconductor chip area while extending beyond its edges. This nested arrangement allows the bridge die to provide enhanced structural support and interconnection reliability without completely occupying additional horizontal space, as portions of the bridge die are positioned over the chip area.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Quantity of substance

If multiple semiconductor chips are stacked to increase capacity, then memory capacity increases, but interconnection reliability becomes difficult to guarantee

Engineering Contradiction:
Improvememory capacityVSAvoidinterconnection reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The bridge die acts as an intermediary substrate between stacked semiconductor chips, providing a stable mechanical and electrical interface. The redistribution layers and conductive structures within the bridge die mediate the interconnections between multiple chips, ensuring reliable signal transmission and power delivery across the stacked configuration while enabling increased memory capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250226360A1Semiconductor package
Publication Date: 2025.07.10 SAMSUNG ELECTRONICS CO LTD
  • US20250226360A1 patent drawing
  • US20250226360A1 patent drawing
  • US20250226360A1 patent drawing

AI summary

A semiconductor package includes a first semiconductor chip including a semiconductor substrate and upper bonding pads disposed on an upper surface of the semiconductor substrate, and a bridge die disposed on the first semiconductor chip, and including a bridge substrate and first lower pads. The bridge substrate includes a first bridge portion and a second bridge portion. The first lower pads are disposed on a first lower surface of the first bridge portion of the bridge substrate and contact the upper bonding pads of the first semiconductor chip, respectively. When viewed in a plan view, the first bridge portion overlaps an edge portion of the first semiconductor chip and the second bridge portion extends beyond a side of the first semiconductor chip in a direction away from the edge portion of the first semiconductor chip. The bridge die and the first semiconductor chip are different types of semiconductor devices.