Semiconductor Package Layout With Bridge Die for Dense 3D Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and functionality in semiconductor devices while maintaining a small footprint, particularly in Package-on-Package (PoP) technology, where efficient packaging techniques are needed to accommodate multiple semiconductor devices with enhanced performance and reduced signal transmission paths.
Innovation Solution
A semiconductor device package structure utilizing fan-out wafer-level packaging (FOWLP) with epoxy molding compound (EMC) and copper bumps, combined with through-mold via structures and redistribution layers, allows for the integration of multiple semiconductor devices and bridge dies, enabling efficient electrical connections and heat dissipation through TSV structures and copper bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and device functionality are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional packaging to three-dimensional stacked packaging with multiple redistribution structures at different heights. The first redistribution structure is disposed on a first side of the second redistribution structure, enabling vertical integration and significantly increasing device density by utilizing the third dimension.
Solution Approach 2:
The patent implements nested packaging where the first semiconductor device is disposed on the first redistribution structure, the second semiconductor device is disposed on the second redistribution structure, and the third semiconductor device is disposed on the second side of the second redistribution structure. This nested arrangement maximizes space utilization and integration density.
2Productivity
If device size is reduced to increase integration density, then more devices fit in given area, but heat dissipation becomes more challenging
Solution Approach 1:
The patent segments the package structure into multiple independent redistribution structures (first and second redistribution structures) with semiconductor devices disposed at different locations and heights. This segmentation creates distributed thermal pathways, preventing heat concentration and improving overall heat dissipation efficiency while maintaining high device density.
3Adaptability or versatility
If signal paths are lengthened to connect multiple devices, then connectivity is achieved, but signal transmission efficiency decreases
Solution Approach 1:
The patent utilizes vertical stacking and three-dimensional arrangement of redistribution structures to create short signal paths between semiconductor devices. By disposing devices and redistribution structures at different heights and positions, the signal transmission distance is minimized while maintaining comprehensive connectivity among all devices in the package.
Data Source
AI summary
A semiconductor device package structure is provided, including a redistribution structure, a first semiconductor device, a second semiconductor device, a bridge die, a first conductive bump, and a second conductive bump bumps, a third conductive bumps, and a first solder material. The first semiconductor device is disposed on a first side of the redistribution structure, the second semiconductor device and the bridge die are disposed on a second side opposite to the first side. The first conductive bump is disposed on the first semiconductor device, the second conductive bump is disposed on the second side of the redistribution structure and the third conductive bump is disposed on the second semiconductor device. The first solder material is electrically connected between the second conductive bump and the third conductive bump, and the redistribution structure is electrically connected between the first conductive bump and the second conductive bump.