Bridge Die Package Structure for High-Density Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging of electronic components due to limitations in feature size reduction and packaging technologies, particularly in forming reliable and compact 3D packaging structures that minimize area usage and maximize integration.
Innovation Solution
The method involves forming a bridge die with through-substrate vias and conductive vias of larger size than the TSVs, embedded in a semiconductor substrate, and encapsulating them with an encapsulant layer to create a conductive via structure, which allows for increased landing window for via alignment and reduces warpage, enabling high-speed connections between device dies while maintaining reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias and conductive vias of larger size are used, then manufacturing precision and reliability are improved, but area usage increases
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical stacking architecture. Multiple device dies are stacked vertically and connected through through-substrate vias that penetrate the substrate thickness direction. This dimensional change allows high-density interconnections without increasing the lateral package footprint, resolving the contradiction between connection reliability and area usage.
Solution Approach 2:
The patent implements nested structures where through-substrate vias are positioned within the substrate thickness, conductive vias are embedded within device dies, and encapsulant layers surround and protect the entire stacked structure. This nested arrangement maximizes space utilization and enables reliable high-speed connections while maintaining compact package dimensions.
2Productivity
If feature size is reduced to increase integration density, then productivity is improved, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent segments the integrated circuit into multiple separate device dies that are stacked vertically. Each die can be manufactured independently using conventional fabrication processes with established precision capabilities. The through-substrate vias provide robust physical and electrical connections between segments, enabling high overall integration density without requiring excessively small features on individual dies, thus maintaining manufacturability.
3Volume of stationary object
If compact packaging is implemented to reduce area, then volume efficiency is improved, but warpage control becomes more difficult
Solution Approach 1:
The patent employs composite material structures including substrate materials, device die materials, encapsulant materials, and conductive via materials with different mechanical and thermal properties. The encapsulant layer acts as a compliant material that absorbs thermal expansion mismatches and mechanical stresses between the rigid substrate and device dies, reducing warpage while maintaining compact package volume.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the package. The encapsulant layer provides localized stress relief around the through-substrate vias and device dies, while the substrate provides rigid support in other areas. This spatial variation in material quality enables compact packaging while controlling warpage through localized stress management.
Data Source
AI summary
A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.